Parallel processing unit which processes branch instructions wit

Details Parallel processing unit which processes branch instructions wit Parallel processing unit which processes branch instructions wit

1996-01-30

1998-09-15

Shah, Alpesh M.

Boots, shoes, and leggings

395581, 395582, 395584, 395586, 364DIG1, G06F 938

Patent

active

058092943

ABSTRACT:
A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in the branch-delay slot are those fetched in a period from fetching of the branch instruction till the execution of the branch instruction. Instructions are prefetched from an instruction memory into a queue memory. The queue memory includes a plurality of blocks of storage units. Instructions in the same block as a branch instruction and subsequent to the branch instruction, and instructions in the block adjacent to the block including the branch instruction provide the branch delay slot for the branch instruction. A parallel processing unit operable in a predicted branch method includes a queue memory including a plurality of entries, each of which includes an instruction and a flag indicating that an associated instruction is executed according to a prediction of a branch. This flag is utilized to control execution and non execution of an associated instruction.

REFERENCES:
patent: 4409654 (1983-10-01), Wada et al.
patent: 4755966 (1988-07-01), Lee et al.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4912635 (1990-03-01), Nishimukai et al.
patent: 4977496 (1990-12-01), Onishi et al.
patent: 5050068 (1991-09-01), Dollas et al.
patent: 5125083 (1992-06-01), Fite et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5142630 (1992-08-01), Ishikawa
patent: 5185869 (1993-02-01), Suzuki
patent: 5261063 (1993-11-01), Kohn et al.
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5287467 (1994-02-01), Blaner et al.
patent: 5333280 (1994-07-01), Ishikawa et al.
patent: 5394529 (1995-02-01), Brown, III et al.
patent: 5440704 (1995-08-01), Itomitsu et al.
Japanese Office Action.
Low-Level Parallel Processing Algorithms for the SIMP Processor Prototype, Feb. 2, 1989, JSPP 89.
Hwang, K.; Briggs F.A.: Computer Architecture and Parallel Processing, New York, etc.: McGraw-Hill Book Company, 1984, pp. 187-193.
German Office Action dated Feb. 13, 1997 and translation thereof.
"The i960 Super Scaler Implementation of the 80960 Architecture" by S. McGready, 1990 IEEE, pp. 232-240.
"A VLSI RICS" by D.A. Patterson et al., Computer, Sep. 1982 pp. 8-20.
"Computer Architecture: A Quantative Approach", by J.L. Hennessy et al, Morgan Kaufman Publishers, Inc.
"Machine Organization of the IBM RISC System/6000 Processor", G.F. Grohoski, IBM Journal of Research and Development, vol. 34, No. 1., Jan. 1990, pp. 37-58.
Gurindar S. Sohi, "Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelined Computers", IEEE Transactions on Computers, vol. 39, No. 3 (Mar. 1990), pp. 349-359.
Kane, "MIPS R2000 RISC Architecture", 1987, pp. 1-1 to 4-11 and A(1-9).
Pawlovsky et al, "A Concurrent Fault Detection Method for Superscalar Processors", IEEE Jan. 1992, pp. 134-144.

Affiliated with

Also associated with

Rating

Parallel processing unit which processes branch instructions wit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel processing unit which processes branch instructions wit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processing unit which processes branch instructions wit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-101123