Video multiplexing system for superimposition of scalable video

Television – Image signal processing circuitry specific to television – Special effects

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345 28, 345127, 348718, 348564, H04N 974

Patent

active

056801785

ABSTRACT:
A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.

REFERENCES:
patent: 4418343 (1983-11-01), Ryan et al.
patent: 4511965 (1985-04-01), Rajaran
patent: 4858107 (1989-08-01), Fedede
patent: 4862269 (1989-08-01), Sonoda et al.
patent: 4907086 (1990-03-01), Truong
Sony CXK1206AM/ATM, Video Signal Field Memory, pp. 1-40 undated.

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