Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1991-11-29

1993-10-05

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

365194, 36523006, G11C 11407

Patent

active

052511804

ABSTRACT:
In the semiconductor memory composed of divided dynamic memory cell arrays, when a drive signal is supplied to a word line selected by a row decoder, data stored at the memory cells connected to the word line are transferred to bit lines, respectively. A change in potential at the bit line pair is amplified by the sense amplifier to completely read the data. To prevent the bit line pairs from being sensed erroneously due to fluctuation of the timings at which the word line driving signals are generated in the divided cell arrays, a bit line sense signal is generated a predetermined delay time after all the word line driving signals have been generated, in order to drive all the sense amplifiers simultaneously, so that data can be definitely read from the memory cells to the bit lines. To detect that all the word line driving signals have been generated, a drive signal detection section is connected between word line driving circuits for all the divided cell arrays and a delay circuit connected to a sense amplifier driving circuit.

REFERENCES:
patent: 4803665 (1989-02-01), Kasa
patent: 4839868 (1989-06-01), Sato et al.
patent: 4933907 (1990-06-01), Kumanoya et al.
IBM Technical Disclosure Bulletin, vol. 33, No. 6B, Nov. 1990, N.Y., U.S., pp. 68-69; "Worldwide Sampling Technique for High Speed CMOS DRAMs".
IBM Technical Disclosure Bulletin, vol. 29, No. 6, Nov. 1986, N.Y., U.S., pp. 2650-2651, "Word Line Detector Circuit".

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