Method of forming an integrated circuit structure with multiple

Details Method of forming an integrated circuit structure with multiple Method of forming an integrated circuit structure with multiple

1988-08-15

1991-09-03

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437190, 437173, 437907, 437908, 148DIG91, 148DIG92, 148DIG93, H01L 2144, H01L 2148, H01L 2160

Patent

active

050455010

ABSTRACT:
An integrated circuit structure and method of forming the same is described in which a plurality of common signal planes are provided for an integrated circuit formed on a layer of semiconductive material (30). The common planes consist of a single crystal semiconductive substrate (2) and at least one conductive layer (26, 66) between the substrate (2) and the semiconductive circuit layer (30), with insulative layers (24, 28, 68) separating the conductive layers (26, 66) from each other and from the substrate (2) and semiconductive layer (30). When one conductive layer (26) is used, a power supply signal (V+) is preferably applied to the substrate (2) and a ground reference to the conductive layer (26). Contacts are made between the integrated circuit and the desired common planes by metallized contacts (56, 60) formed in openings (54, 58) through the underlying material. Various circuit signals can also be introduced through additional conductive layers. In either case, only the top layer of semiconductive material (30) needs to be recrystallized from the substrate (2) into single crystal form, even if the conductive layers (26, 66) are provided as heavily doped semiconductive materials. The novel structure greatly reduces the surface area devoted to metallization, and practically eliminates cross-talk between components. It also enables a reduction of metallization levels from two to one, significantly increasing circuit yield.

REFERENCES:
patent: 4424579 (1984-01-01), Roesmer
patent: 4472729 (1984-09-01), Shibata et al.
patent: 4487635 (1984-12-01), Kugimiya et al.
patent: 4536785 (1985-08-01), Gibbons
patent: 4569700 (1986-02-01), Toyama
patent: 4596604 (1986-06-01), Akiyama et al.
patent: 4604159 (1986-08-01), Kobayashi et al.
patent: 4920072 (1990-04-01), Keller et al.
patent: 4975386 (1990-12-01), Rao
patent: 4977105 (1990-12-01), Okamoto et al.

Affiliated with

Also associated with

Rating

Method of forming an integrated circuit structure with multiple does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming an integrated circuit structure with multiple , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an integrated circuit structure with multiple will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1009184