Method of making integrated circuit with high current transistor

Details Method of making integrated circuit with high current transistor Method of making integrated circuit with high current transistor

1989-09-25

1991-09-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 63, 437 69, 437 31, 148DIG86, H01L 2176

Patent

active

050454927

ABSTRACT:
A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from 950.degree. C. to 1100.degree. C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping. This results in close self-alignment of the N+ plugs and their associated DMOS and NPN transistors leading to low on-resistance, to higher IC component density, to a high throughput rate at manufacturing and low cost.

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R. A. Colclaser, Microelectronics: Processing and Device Design, 1980, pp. 128-129.

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