Method of making a pleated floating gate trench EPROM

Details Method of making a pleated floating gate trench EPROM Method of making a pleated floating gate trench EPROM

1990-08-21

1991-09-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437 48, 437 49, 437 50, 437 52, 437195, H01L 21265

Patent

active

050454900

ABSTRACT:
One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.

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