Method of making a high-speed 2-transistor cell for programmable

Details Method of making a high-speed 2-transistor cell for programmable Method of making a high-speed 2-transistor cell for programmable

1989-06-30

1991-09-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437 49, 437 50, 437 52, 437 61, 357 235, H01L 21265

Patent

active

050454897

ABSTRACT:
A 2-transistor cell (26) comprises buried diffused regions (34, 36 and 38) aligned substantially parallel. Floating gates (40) are aligned substantially perpendicular to the diffused regions (34, 36 and 38). A control gate (42) defines a first channel region between first and second diffused regions (34 and 36) to define a read transistor (30) and a second channel region between second and third diffused regions (36 and 38) to define a program transistor. The read transistor (30) and program transistor (32) may be individually optimized according to their respective functions. Further, tunnel windows (70) may be provided for Fowler-Nordheim tunneling.

REFERENCES:
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patent: 4372031 (1983-02-01), Tsaur et al.
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4379343 (1983-04-01), Moyer
patent: 4467453 (1984-08-01), Chiu et al.
patent: 4628487 (1986-12-01), Smayling
patent: 4780424 (1988-10-01), Holler
"A 19-ns 250-mW CMOS Eraseable Programmable Logic Device", by Pathak et al., IEEE Journal of Solid State Circuits, vol. 5C-21, No. 5, Oct. 1986, pp. 775-784.

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