Register and instruction controller for superscalar processor

Details Register and instruction controller for superscalar processor Register and instruction controller for superscalar processor

1995-10-06

2000-12-26

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

G06F 922

Patent

active

061675032

ABSTRACT:
In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.

REFERENCES:
patent: 4775932 (1988-10-01), Oxley et al.
patent: 5490280 (1996-02-01), Gupta
patent: 5535346 (1996-07-01), Thomas
patent: 5574935 (1996-11-01), Vidwans et al.
United States Patent 5,530,817; Jun. 25, 1996.
Franklin et al., The Expandable Split Window Paradigm for Exploiting Fine-Grained Parallelism, Computer Architecture News, No. 2, May 20, 1992, pp. 58-67.
International Publication #WO 95/09394, Apr. 6, 1995, World Intellectual Property Organization, pp. 1-58 with drawings.
Keckler et al., Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism, Proceedings of the Annual International Symposium on Computer Architecture, Gold Coast, Australia, May 19-21, 1992, No. SYMP 19, May 19, 1992, Institute of Electrical and Electronics Engineers, pp. 202-213.
Hunt, Advanced Performance Features of the 64-bit PA-8000, Digest of Papers of the Computer Society Computer Conference (Spring) Compcon, Technologies for the Information Superhighway San Francisco, Mar. 5-9, 1995, No. Conf. 40, Mar. 5, 1995, Institute of Electrical and Electronics Engineers, pp. 123-128.
Fossum et al., Designing a VAX for High Performance, Computer Society International Conference (Compcon), Spring Meeting, Los Alamitos, Feb. 26-Mar. 2, 1990, no. Conf. 35, Feb. 26, 1990, Institute of Electrical and Electronics Engineers, pp. 36-43.
Palacharla et al., Decoupling Integer Execution in Superscalar Processors, Proceedings of the 28.sup.th Annual International Symposium on Microarchitecture, Ann Arbor, Nov. 29-Dec. 1, 1995, no. Symp. 28, Nov. 29, 1995, Institute of Electrical and Electronics Engineers, pp. 285-290.
James E. Smith, "Dynamite Instruction Scheduling and the Astronautics ZS-1", IEEE Jul. 1989, pp. 21-34.

Affiliated with

Also associated with

Rating

Register and instruction controller for superscalar processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Register and instruction controller for superscalar processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Register and instruction controller for superscalar processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1006646