Isolation using self-aligned trench formation and conventional L

Details Isolation using self-aligned trench formation and conventional L Isolation using self-aligned trench formation and conventional L

1995-06-22

1997-10-21

Dang, Trung

Fishing, trapping, and vermin destroying

437 70, 437 67, 437 72, H01L 2176

Patent

active

056795998

ABSTRACT:
A method for isolating regions of a circuit device in a semiconductor substrate. The method generally comprises the steps of: forming a first insulation region and a second insulation region; etching a trench in the first insulation region, the trench extending into the semiconductor substrate to a depth below the surface of the semiconductor substrate; filling the first isolation region with an isolation material and removing a portion of the isolation material such that the trench isolation material fills the trench and has a surface level with the surface of the substrate; and thermally growing a field oxide in the first and second isolation regions. In a further aspect, a semiconductor device is provided. The device is formed on a semiconductor substrate, the substrate having a surface and includes at least a first, second, and third active regions separated by first and second insulating regions. The first insulation region separates the first and second active regions, and includes a first portion extending a first depth into the semiconductor substrate and having a width, and a second portion extending a second depth into the semiconductor substrate and having a second width. In the first insulating region, the first depth is greater than the second depth and the first width is smaller than the second width. The second insulating region separates the second and third active regions, and has a third width and extending a third depth below the surface of the semiconductor substrate, the third depth being substantially the same as said second depth.

REFERENCES:
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patent: 5130268 (1992-07-01), Liou et al.
patent: 5438016 (1995-08-01), Figura et al.
patent: 5472904 (1995-12-01), Figura et al.
patent: 5498566 (1996-03-01), Lee
Park, et al., "Self-Aligned LOCOS/Trench (SALOT) Combination Isolation Technology Planarized by Chemical Mechanical Polishing", IEDM Technology Digest, pp. 675-678, 1994.

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