Method of making raised-bitline contactless trenched flash memor

Details Method of making raised-bitline contactless trenched flash memor Method of making raised-bitline contactless trenched flash memor

1996-12-16

1997-10-21

Niebling, John

Fishing, trapping, and vermin destroying

437 52, H01L 218247, H01L 21265

Patent

active

056795912

ABSTRACT:
A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes. Source/drain regions are formed in the second well self-aligned with the stacks as well as spacer dielectric structures formed adjacent to the sidewalls of the stacks. A third doped polysilicon layer patterned into raised bitlines overlies source/drain regions.

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Y. Hisamune et al. "A 3.6um.sup.2 Memory Cell Structure for 16MB EPROMS", IEDM (1989) pp. 583-586, month unknown.

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