Method of forming a buried bit line array of memory cells

Details Method of forming a buried bit line array of memory cells Method of forming a buried bit line array of memory cells

1992-02-19

1993-10-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 50, 437 52, H01L 2170, H01L 2700

Patent

active

052504573

ABSTRACT:
A method of forming a buried bit line array of memory cells comprises: a) providing an array of word lines atop a semiconductor wafer; b) providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; c) providing a layer of first material (preferably polyimide) atop the wafer to a selected thickness; d) patterning and etching the layer of first material to define a pattern of buried bit line grooves for formation of buried bit lines therewithin, the bit line grooves having a first selected width; e) providing a layer of insulating material to a selected thickness atop the wafer over the patterned and etched layer of first material, the selected thickness of insulating material being less than half the first selected width, the layer of insulating material narrowing the bit line grooves to a smaller second width; f) providing bit line contact openings to second active regions within and at the bases of the second width bit line grooves; g) conductively doped polysilicon and on overlying higher conductive material are provided within the grooves for bit line formation; h) an array of capacitors are provided atop the wafer which electrically engage with first active regions.

REFERENCES:
patent: 4987099 (1991-01-01), Flanner
patent: 5023683 (1991-06-01), Yanada
patent: 5032882 (1991-07-01), Okumura et al.
patent: 5084414 (1992-01-01), Manley et al.
patent: 5087591 (1992-02-01), Teng
patent: 5120679 (1992-06-01), Boardman et al.
Kawamoto, et al., "A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64 Mb DRAMs," Symposium on VLSI Tech., 1990 IEEE, pp. 13-14.

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