Insulated-gate vertical field-effect transistor with high curren

Details Insulated-gate vertical field-effect transistor with high curren Insulated-gate vertical field-effect transistor with high curren

1992-02-12

1993-10-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 257327, H01L 21265

Patent

active

052504506

ABSTRACT:
An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portions of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

REFERENCES:
patent: 4116720 (1978-09-01), Vinson
patent: 4199774 (1980-04-01), Plummer
patent: 4272302 (1981-06-01), Jhabvala
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4364073 (1982-12-01), Becke et al.
patent: 4364074 (1982-12-01), Garnache et al.
patent: 4374455 (1983-02-01), Goodman
patent: 4464212 (1984-08-01), Bhatia et al.
patent: 4476622 (1984-10-01), Cogan
patent: 4503598 (1985-03-01), Vora et al.
patent: 4543706 (1985-10-01), Bencuya et al.
patent: 4566172 (1986-01-01), Bencuya et al.
patent: 4567641 (1986-02-01), Baliga et al.
patent: 4650544 (1987-03-01), Erb et al.
patent: 4683643 (1987-08-01), Nakajima et al.
patent: 4689871 (1987-09-01), Malhi
patent: 4758528 (1988-07-01), Goth et al.
patent: 4859622 (1989-08-01), Eguchi
patent: 4920065 (1990-04-01), Chin et al.
Krishna Shenai, A 55-V, 0.2-m.OMEGA.. cm.sup.2 Vertical Trench Power MOSFET, IEEE Electron Device Letters, vol. 12 No. 3, Mar. 1991, pp. 108-110.
Tadahiro Ohmi, Power Static Induction Transistor Technology, IEEE Paper, Catalog No. CH1504-0/79/0000-0084 pp. 84-87 (1979).
Nicky C. C. Lu, Advanced Cell Structures for Dynamic RAMs, IEEE Circuits and Devices Magazine, Jan. 1989, pp. 27-36.

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