Method and circuit for delayed branch control and method and cir

Details Method and circuit for delayed branch control and method and cir Method and circuit for delayed branch control and method and cir

1998-07-22

2000-04-25

Treat, William M.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712217, 712234, G06F 938

Patent

active

060556269

ABSTRACT:
In a processor employing a delayed branch method, delayed branch control which does not complicate instruction execution sequence and improves the readability of a program on the assembler level is implemented without providing a control bit in an instruction code. The delayed branch control according to the present invention involves the use of a branch-information storing circuit for storing the occurrence or nonoccurrence of a branch in a specified one of a continuous sequence of cycles immediately before a current execute cycle which are equal in number to delay slots in the processor. In executing a delayed branch instruction, when the branch-information storing circuit stores the occurrence of a branch in the specified cycle, a branch is disabled. This prevents instruction execution sequence from being complicated even when individual branch conditions for consecutive delayed branch instructions are satisfied, so that the program on the assembler level is improved in readability. The branch-information storing circuit can simply be composed of a combination of a shift register, a counter, and a latch.

REFERENCES:
patent: 3760365 (1973-09-01), Kurtzberg et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5487156 (1996-01-01), Popescu et al.
Sun Microsystems Inc., "Spark Architecture Manual", The SPARC Architecture Manual, Version 8, Jan. 30, 1991, pp. 43-48.
J. Cortadella et al.: "Designing a Branch Target Buffer for Executing Branches With Zero Time Cost in a RISC Processor", Microprocessing & Microprogramming, vol. 24, No. 1-6, Aug, 1988, pp. 573-580, XP000038090.
A.M. Gonzalez: "A survey of branch techniques in pipelined processors" Microprocessing & Microprogamming, vol. 36, No. 5, Oct. 1993, pp. 243-257, XP000397907.
M. J. Mahom et al: "Hewlett-Packard Precision Architecture: The Processor" Hewlett-Packard Journal, vol. 37, No. 8, Aug. 1986, pp. 4-21, XP000211314.
G.B. Steven, et al., "ALU Design and processor branch architecture" Microprocessing and Microprogramming, vol. 36, No. 5, Oct. 1993, Amsterdam, NL, pp. 259-278.
J.A. Derosa, et al., "An Evaluation of Branch Architectures", Proceedings fo the 14th Annual International Symposium of Computer Architecture, Jun. 2-5, 1987, Pittsburgh, PA, US, pp. 10-16.

Affiliated with

Also associated with

Rating

Method and circuit for delayed branch control and method and cir does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit for delayed branch control and method and cir, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for delayed branch control and method and cir will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1002912