Store-to-load hazard resolution system and method for a processo

Details Store-to-load hazard resolution system and method for a processo Store-to-load hazard resolution system and method for a processo

1996-03-01

1998-09-15

Lall, Parshotam S.

395591, G06F 900

Patent

active

058092757

ABSTRACT:
A store-to-load (ST/LD) hazard resolution system for resolving conflicts produced from ST/LD instruction dependencies and out of order execution of instructions in a processor. The ST/LD hazard resolution system involves the following components. A fetch mechanism (IFETCH) fetches instructions from an instruction cache (ICACHE). A memory instruction queue (MQUEUE) receives instructions that are directed to a data cache (DCACHE) or a main memory from the IFETCH and executes the instructions out of order. The MQUEUE includes instruction registers and corresponding address reorder buffer slots (ARBSLOTs) for receiving memory instructions and data addresses corresponding to the results of instruction execution, respectively. A ST/LD hazard resolution system is associated with each ARBSLOT for recognizing and tracking ST/LD dependencies among the memory instructions. When a load instruction depends upon a store instruction and the load instruction is unexecuted, then the load instruction is put on hold until the store instruction is executed and cleared. When the dependent load instruction is already executed, then the ST/LD hazard resolution system associates a panic trap indicator with the executed load instruction. After an instruction is executed in the MQUEUE, it is retired by a retire mechanism. During the retirement process, upon recognizing a panic trap indicator, a trap vector generator associated with the retire mechanism purges instructions from the MQUEUE and causes the IFETCH to recommence fetching, beginning with the panic trapped instruction.

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