4. Electrical computers and digital processing systems: memory
  5. Storage accessing and control
  6. Hierarchical memories

Stuart C. Siu

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Method and apparatus for sequencing and decoding variable length

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Streamlined cache coherency protocol system and method for a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1397743

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