Multiple level floating-gate memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185030, C365S185200

Reexamination Certificate

active

06404679

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a multiple-level floating-gate memory, and more particularly, the invention relates to a memory in which the basic storage element is a floating-gate transistor that must store a piece of information whose value can take one of at least three states.
BACKGROUND OF THE INVENTION
Multiple-level floating gate memories are used to increase storage capacity without increasing the surface area of the storage matrix. This principle has been disclosed, for example, in the applications EP-A-0 340 107 (D1 here below) and EP-A-0 656 628 (D2 here below). The standard memories generally store one bit, namely two electrical levels, per storage element. The multiple-level memories store a larger number of electrical levels. Thus, when a multiple-level memory with four electrical levels is made, this allows the storage of two bits per storage element, the storage capacity in this case being doubled for one and being the same matrix size.
To obtain the different electrical levels, the floating gate of the storage transistor is charged in varying degrees. The gate that is charged in varying degrees has the effect of bringing about a variation in the conduction threshold voltage of the storage transistor. In order to write in such cells, a sequence of programming/reading/verification cycles is performed until the desired programming level is obtained. The reading is done by applying a read voltage to the storage transistor which makes this transistor more conductive or less conductive depending on the charge present at the floating gate. The channel of the storage transistor is connected to a load which converts the current flowing through the storage transistor into a voltage. The voltage is then compared to different thresholds to determine the stored state.
However this type of memory has drawbacks. Two of these drawbacks are, firstly, high power consumption and, secondly, risk of deterioration of the data. The high consumption is due, inter alia, to the voltages and currents used during reading operations. Indeed, during a reading operation, the transistors are biased to obtain different currents in their drain-source channel, with the current representing the stored information. Now, to have better readability of the different values stored, read currents are used with values three times greater than in the case of standard floating-gate memories.
The structure of a multiple-level memory matrix is the same as that of a standard memory matrix.
FIG. 1
shows the current-voltage curve of a bit line with a given basic bias voltage. The curve of
FIG. 1
results from different programming levels for a given bias of the bit line. The reading is then done either in current or in voltage. The currents IR
1
, IR
2
and IR
3
represent the current thresholds that differentiate the storage levels. For further details, those skilled in the art may refer, for example, to D
1
.
The risk of deterioration of the data arises from the use of several data thresholds which increases the risks of deterioration of the data stored in a floating-gate transistor. The risk of deterioration of the data is also increased by the greater electrical stress undergone by each storage transistor. Indeed, the use of several programming levels requires the use of a substantial gate bias voltage (of about 4 to 6 volts). This favors charge migrations. The phenomenon is further accentuated during the reading of a highly conductive storage transistor.
FIG. 2
shows an example of characteristic curves of current going through the channel of a storage transistor as a function of the bias voltage, for the storage thresholds. In this example, the threshold current IR
3
corresponds substantially to the conduction current of the storage transistor at the beginning of the state when the conduction is linear. This current IR
3
corresponds to the threshold current used for a binary type of memory. Those skilled in the art can see that the spacings between the characteristics corresponding to the different thresholds do not follow a linear pattern. This stepped feature is partly due to the stress on the memories. Indeed, the first threshold characteristic
1
corresponds to the characteristic curve used for a binary type memory. It is difficult to shift this characteristic because it is far too low. This leads to a continuous conduction of the storage transistor (giving rise to malfunctioning for Flash-EEPROM type memories).
The second and third characteristics
2
and
3
are shifted to have high readability between the programming levels. Furthermore, to obtain a reading, it is appropriate to bias the bases of the storage transistors at a voltage such that all the programming levels can be read. The bias voltage therefore corresponds to the voltage that produces the threshold current IR
3
for the third characteristic
3
. This bias voltage brings about a correspondence of the bigger currents for the first and second characteristics
1
and
2
.
In the example shown, the bias voltage is set at 4.5 VT with VT corresponding to the conduction voltage of an N channel MOS transistor, namely about 1.1 V. Now this bias voltage corresponds to about half the erasure voltage (or programming voltage) of certain storage transistors. Those skilled in the art will appreciate that the current flowing in the channel of the transistors whose programming corresponds to the levels “
11
” or “
10
” is fairly great and that a low-amplitude Fowler Norheim effect can occur. The likelihood of this effect occurring increases as the programming level is low, and has the effect of lowering the programming threshold. To prevent this, the programming levels are further spaced out as they are low. The transistors whose programming level is lower than the first characteristic (level
11
) are the most subject to reading stress. In the case of a Flash-EEPROM memory, a depletion phenomenon (giving rise to an always-on transistor) may make the memory unusable.
In D
1
and D
2
, the different approaches are presented to limit the risks of use. D
1
proposes the use of several reading thresholds, some of which can be used to verify that the writing has been rightly done while others can be used to carry out a reading operation. The thresholds that can be used for the verification of reading are more restrictive that they are for simple read operations. D
2
proposes a memory refresh device to compensate for programming drifts.
SUMMARY OF THE INVENTION
To overcome these problems, the invention proposes to limit the bias voltage and the current flowing in a storage transistor. Thus, according to the invention, the reading is done by a gate bias voltage that is equal to the voltage needed to obtain a predetermined reference current in the selected storage transistor. The decoding of the stored piece of data being done by the decoding of the bias voltage. Thus, the invention reduces the current flowing through the transistors during the reading, and reduces the basic biasing electrical stress undergone during each reading.
An object of the invention is to provide an integrated circuit comprising a memory that includes a plurality of bit lines, a plurality of word lines, and a plurality of floating-gate transistors placed at the intersections of the word lines and the bit lines. Each floating-gate transistor stores an electrical state representing a stored piece of data. The memory also includes at least one circuit to compare a current flowing through a selected bit line with a reference current, a voltage generator circuit that generates a growing bias voltage to a gate of at least one floating-gate transistor so long as the current flowing through the bit line is smaller than the reference current, and a decoding circuit that outputs digital information representing the stored piece of data by decoding the value of the bias voltage.
Another object of the invention is also a method for the reading of a memory comprising a plurality of bit lines, a plurality of word lines, and a plurality of floating-gate transistors placed a

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