Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-21
2001-09-25
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S303000
Reexamination Certificate
active
06294422
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a plurality of active region groups and contact areas formed for each of the plurality of active region groups and a method for manufacturing the same. Further, the present invention relates to a semiconductor device which has first and second regions having a plurality of MOS transistors formed and arranged therein and in which distances between gate electrodes and impurity concentrations of diffusion layers are different in the first and second regions and a method for manufacturing the same.
The integration density and the capacity of a semiconductor memory device are steadily increased. Particularly, the integration density of a DRAM having memory cells each constructed by one MOS transistor and one capacitor is most rapidly increased because of the memory cell form thereof.
With an increase in the integration density, the area of a memory cell continues to be reduced. As a result, in the DRAM, the area of the charge storage electrode is reduced and the amount of storage charges is reduced, thereby making it difficult to correctly read out a memory signal. Further, it becomes difficult to control the MOS transistor region and element isolation region.
In order to solve the above problem, a DRAM using memory cells (stack type memory cells) each having a structure in which storage charge electrodes are formed on bit lines is proposed.
FIG. 1
is a plan view showing the above type of conventional DRAM, and
FIGS. 2A
to
2
C are cross sectional views of the DRAM.
FIG. 2A
is a cross sectional view taken along a line extending across the active regions and in parallel to the bit line,
FIG. 2B
is a cross sectional view taken along a line extending across bit line plug electrodes and in parallel to the word line WL, and
FIG. 2C
is a cross sectional view taken along a line extending across storage charge plug electrodes and in parallel to the word line WL.
In the drawings,
171
denotes a silicon substrate,
171
a
an active region,
172
an element isolation insulating film,
173
a gate insulating film,
174
a gate electrode,
175
a gate upper/side-wall insulating film,
1761
a bit line plug electrode,
1762
a storage charge plug electrode,
177
an inter-level insulating film,
178
a bit line upper/side-wall insulating film,
179
a storage charge electrode,
180
a capacitor insulating film, and
181
a plate electrode. In the drawing, source and drain electrodes are omitted.
In the above DRAM, the bit line plug electrode
1761
of a pattern as shown in FIG.
3
and the active regions
171
a
of a pattern as shown in
FIG. 4
are used. In
FIG. 5
, a pattern obtained by superposing them is shown.
In order to form the active regions
171
a
shown in
FIG. 4
by use of a resist pattern, it is necessary to transfer an exposure mask pattern having projecting portions on the resist. However, since it is difficult to accurately transfer the above pattern on the resist, it is impossible to form the memory cells as designed and it is difficult to attain the high integration density.
FIG. 6
is a plan view of a DRAM using other conventional stack type memory cells and
FIGS. 7A
to
7
C are cross sectional views of the DRAM.
FIGS. 8
to
10
are views corresponding to
FIGS. 3
to
5
.
In this type of DRAM, since the active region
171
a
is rectangular as shown in
FIG. 9
, a resist pattern can be formed by use of an exposure mask pattern having no projecting portion. However, since the bit line plug electrode
1761
has a projecting portion as shown in
FIG. 8
, the resist pattern is formed by use of an exposure mask pattern having projecting portions. Therefore, like the former DRAM, it is impossible to form the memory cells as designed and it is difficult to attain the high integration density.
In order to meet the requirement of high integration density and high-speed operation, it is proposed to form the DRAM and a logic device on the same chip. However, if the integration density is further enhanced, it becomes difficult to simultaneously form the DRAM and logic device.
It becomes particularly difficult to simultaneously form MOS transistors of the DRAM and MOS transistors of the logic device. This is because gate side-wall insulating films having different film thicknesses are present. That is, in the MOS transistors in the peripheral area of the DRAM and those of the logic device, the gate side-wall insulating films are made thick in order to enhance the performance thereof, and in the MOS transistors in the memory area of the DRAM, the gate side-wall insulating films are made thin since the wiring pitch (distance between gate electrodes) of the gate wirings (gate electrodes) is small.
In order to solve the above problem, the following process is proposed.
First, as shown in
FIG. 11A
, insulating films
202
are filled in trenches formed in the surface portion of a p-type silicon substrate
201
by a known method to attain element isolation, and then, gate oxide films
203
, gate electrodes
204
and gate cap insulating films
205
are formed in a memory cell area and an area (which is hereinafter referred to as a peripheral area) in which the distance between the gate electrodes is longer than that in the memory cell area.
Next, as shown in
FIG. 11B
, n-type impurity ion is implanted into the substrate surface with the gate cap insulating films
205
used as a mask so as to form n-type source/drain diffusion layers
206
and then first gate side-wall insulating films
207
with a thickness for the MOS transistors in the memory cell area are formed.
Next, as shown in
FIG. 11C
, second gate side-wall insulating films
208
are formed to form gate side-wall insulating films with a thickness for the MOS transistors in the peripheral area. That is, the gate side-wall insulating films with a thickness for the MOS transistors in the peripheral area are completed by formation of the first and second gate side-wall insulating films
207
,
208
. In this case, as a material for the second gate side-wall insulating film
208
, a material which does not cause the first gate side-wall insulating film
207
to be made thin at the time of etching of the second gate side-wall insulating film
208
is selected.
Next, as shown in
FIG. 11C
, n-type source/drain diffusion layers
210
of high impurity concentration are selectively formed in the peripheral area by ion-implantation with the memory cell area covered with a resist pattern
209
. After this, the resist pattern
209
is removed.
Then, as shown in
FIG. 12A
, an inter-level insulating film
211
is formed. For example, a CMP process is effected for planarization for the inter-level insulating film
211
.
Next, as shown in
FIG. 12B
, a resist pattern
212
is formed and the inter-level insulating film
211
on the n-type source/drain regions
206
is selectively etched out with the resist pattern
212
used as a mask, and then, as shown in
FIG. 12A
, the second gate side-wall insulating films
208
on the n-type source/drain regions
206
is selectively etched out. Thus, the gate side-wall insulating films having different film thicknesses in the memory cell area and in the peripheral area are completed. After this, the resist pattern
212
is removed.
Next, as shown in
FIG. 12C
, source/drain electrodes
213
are formed in the memory cell area. A concrete method for forming the source/drain electrodes
213
is described below.
First, a conductive film for formation of the source/drain electrodes
213
is formed on the entire surface by a film forming method such as a CVD method. Then, the conductive film is heated to make the surface condition thereof uniform. Finally, the entire surface of the conductive film is etched back or set back to the cap insulating film
205
by a method such as an etching or CMP process. The process effected after the step of forming the source/drain electrodes
213
is the same as the process which is well known in the art.
This type of method has the following problem.
In this method, the n-type
Aoki Masami
Sunouchi Kazumasa
Banner & Witcoff , Ltd.
Chaudhuri Olik
Kabushiki Kaisha Toshiba
Pham Hoai
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