Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-24
2001-07-31
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S408000, C257S390000, C257S393000, C257S365000, C257S368000
Reexamination Certificate
active
06268627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device ensuring stable operation of a memory cell.
2. Description of the Background Art
As an example of a conventional semiconductor device, a semiconductor device provided with a static random access memory (hereinafter referred to as an “SRAM”) will be described. An SRAM is a volatile semiconductor device, in which memory cells are placed at crossings of complementary data lines (bit lines) and word lines arranged in a matrix.
FIGS. 20A and 20B
each show an equivalent circuit of the memory cell. Referring to
FIGS. 20A and 20B
, each memory cell is composed of a flip-flop circuit F and two access transistors A
1
and A
2
. In flip-flop circuit F, one inverter INV
1
having a load element L
1
and a driver transistor D
1
and the other inverter INV
2
having a load element L
2
and a driver transistor D
2
each have its input terminal and output terminal cross-coupled, thereby forming two storage nodes N
1
and N
2
.
Access transistor A
1
has a source region connected to storage node N
1
, and a drain region connected to one of the complementary bit lines. Similarly, access transistor A
2
has a source region connected to storage node N
2
, and a drain region connected to the other bit line of the complementary bit lines. Driver transistor D
1
has a drain region connected (commonly) to the source region of access transistor A
1
, and a source region connected to a ground line V
EE
. The gate electrode of driver transistor D
1
is connected to the source region of access transistor A
2
.
Driver transistor D
2
has a drain region connected (commonly) to the source region of access transistor A
2
, and a source region connected to ground line V
EE
. The gate electrode of driver transistor D
2
is connected to the source region of access transistor A
1
. One end of load element L
1
is connected to the source region of access transistor A
1
, and the other end to a power supply line (V
CC
line). Similarly, one end of load element L
2
is connected to the source region of access transistor A
2
, and the other end to power supply line (V
CC
line).
Gate electrodes of access transistors A
1
and A
2
are connected to a word line (WL), which controls conduction of access transistors A
1
and A
2
. Storage nodes N
1
and N
2
have two stable states in which the voltage of one storage node is at a high level and that of the other node is at a low level, or vice versa. This is called a bistable state, and the memory cell will be kept at this bistable state as long as a prescribed power supply voltage is applied thereto.
The operation of the SRAM will now be described. Firstly, when writing data into a specific memory cell, a word line (WL) corresponding to the memory cell conducts access transistors A
1
and A
2
, and forcefully applies a voltage to a pair of the complementary bit lines according to a desired logic value. The potentials of the two storage nodes N
1
and N
2
of flip-flop circuit F is thus set to the above-described bistable state, with data kept as the potential difference.
For data reading, access transistors A
1
and A
2
are rendered conductive, the potentials of storage nodes N
1
and N
2
are transmitted to the bit lines, whereby data are read out.
Next, input/output transfer characteristics indicating the performance characteristics of the above memory cell will be described with reference to drawings. Firstly,
FIG. 21
shows the input/output transfer characteristics of a pair of inverters shown in FIG.
20
B. In
FIG. 21
, the ordinate represents the potential of storage node N
2
, and the abscissa represents the potential of storage node N
1
. Curved lines C and C
1
show correlations of the inputs and outputs of the pair of inverters. In order for the inverters to function as a flip-flop circuit, curved lines C and C
1
need to have two intersections, i.e., two stable points S
1
and S
2
. Particularly, a memory cell must be designed to have a sufficiently large area surrounded by curved lines C and C
1
to stand up to practical use. Here, the diameter of a circle inscribed in curved lines C and C
1
is used as an indicator, as shown in FIG.
21
. Specifically, the diameter of this circle is called a static noise margin (SNM).
Next,
FIG. 22
shows the input/output transfer characteristics of the memory cell at standby. As access transistors A
1
and A
2
are not conductive at standby, driver transistors D
1
and D
2
and load elements L
1
and L
2
form respective inverters of the memory cell. At this time, load elements L
1
and L
2
have relatively high impedance, whereby the inverter outputs make steep transitions. Therefore, in this case, the static noise margin is relatively large, enabling the data to be kept stably.
Next,
FIG. 23
shows the input/output transfer characteristics of the memory cell at data reading. When reading data out of the memory cell, access transistors A
1
and A
2
are rendered conductive, so that a column current flows into the storage node at a low level. This results in a condition equivalent to that in which a load with a relatively low impedance is connected in parallel to the load element. Thus, load elements L
1
and L
2
with high impedance function as if they did not exist. The inverters are therefore regarded as NMOS enhancement type ones with the access transistors serving as a load. The relation of the inputs and outputs of the inverters at this time is expressed as curved lines C and C
1
, from which it is understood that the inclination of the transition at the inverter outputs is more gentle when it is compared in particular to the inverter outputs at standby. This means that the gain of the inverters at this time is lower than that at standby.
FIG. 24
shows the input/output transfer characteristics of the memory cell at writing data. In the memory cell into which data are to be written, access transistors A
1
and A
2
are rendered conductive, and the voltage of one of the complementary bit lines is lowered closer to a ground potential (which is called “to pull down”) to set the potential of the storage node at a low level.
This will be explained with reference to FIG.
24
. Suppose that the memory cell is initially stabilized at S
2
, i.e., (N
1
, N
2
)=(“L”, “H”). In order to rewrite this data to an opposite data, i.e., (N
1
, N
2
)=(“H”, “L”), the voltage of the bit line connected to access transistor A
2
is pulled down. This results in the change of the input/output transfer characteristics of one of the inverters, which have storage node N
1
as an input and storage node N
2
as an output, from that as expressed by curved line C
1
to that as curved line C
2
. Here, there is only one stable point S
1
′, offering a monostable state, and thus the data is rewritten. When pulling down is stopped to quit data writing, the inverter outputs make transitions to cross point S
1
and are stabilized.
In conventional semiconductor devices, several approaches have been taken to attain stable operation of a memory cell in the above-described SRAM. For example, Japanese Patent Laying-Open No. 4-61377 describes an approach to set the threshold voltage of a driver transistor higher than the threshold voltage of an access transistor. That is, the threshold voltage of the access transistor is set even lower.
This will now be described. Especially when reading data, the potential of the storage node at a high level lowers from the power supply voltage at standby to the power supply voltage minus the threshold voltage of an access transistor, causing a static noise margin temporarily lowered considerably at times. Here, if the inverters do not have a sufficient static noise margin, the bistable state will be lost and thus data will be destructed. In order to prevent this from occurring, the threshold voltage of the access transistor is normally kept low to increase the static noise margin of the inverters, and thus stable operation of the memory cell is ens
Fujii Yasuhiro
Ishigaki Yoshiyuki
Fenty Jesse A
Lee Eddie
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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