Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-07-29
2001-08-07
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S745000
Reexamination Certificate
active
06271142
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor circuitry and, more specifically, to the manufacture of Dynamic Random Access Memory (DRAM) deep trench storage capacitors and buried plates in such capacitors.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) cells within semiconductor circuits typically incorporate deep trench storage capacitors. As the lithographic ground rules used to pattern such deep trench storage capacitors continue to diminish with each successive generation of DRAM technology, it is desired to reduce process complexity and to increase manufacturing tolerances. Buried plate diffusion regions are commonly used to connect the plate region of a deep trench storage capacitor array. Current processes for making such buried plate diffusion regions add process steps and process complexity, however, to the cost-sensitive DRAM manufacturing process.
For example, a standard process for manufacturing DRAM trench capacitor buried plates may comprise:
(a) etching a trench in a surface of a substrate;
(b) forming a barrier layer on the trench side wall;
(c) filling the trench with photoresist;
(d) etching the photoresist to a predetermined depth, controlling the depth by the amount of etch time, the depth defining a filled lower region and an exposed upper region;
(e) removing the barrier layer in the upper region to expose the underlying side wall;
(f) stripping the photoresist;
(g) forming a collar on the side wall upper portion, using the barrier layer as a mask in the lower region; and
(h) forming a buried plate diffusion region in the trench lower region, using the collar as a mask for the upper portion.
The above process, using a photoresist fill and etch step, is commonly called a photoresist recess technique. Because the steps of filling with photoresist and etching add process complexity, it is desirable to simplify and shorten the process for formation of buried plate diffusion regions in deep trench storage capacitors by eliminating the photoresist fill and etch steps.
The deficiencies of the conventional methods used to manufacture DRAM deep trench storage capacitors and buried plates in such capacitors show that a need still exists for an improved process. To overcome the shortcomings of the conventional methods, a new process is provided. An object of the present invention is to simplify and shorten the process for formation of buried plate diffusion regions in deep trench storage capacitors. A related object is to eliminate the photoresist fill and etch steps typically used in conventional methods.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a process for manufacturing a deep trench capacitor in a trench. The capacitor comprises a collar in an upper region of the trench and a buried plate in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material. The process comprises the steps of (a) forming a deep trench in a substrate, the trench having side walls, a bottom, an upper region, and a lower region; (b) filling the trench lower region with the non-photosensitive underfill material, such as spin-on-glass; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
The process of the present invention may be performed sequentially in a first order (a), (b), (c), (d), (e), or in a second order (a), (b), (d), (c), (e). When the process is performed in the first order, step (c) may comprise (i) conformally depositing a dielectric material, such as an oxide or oxynitride, by chemical vapor deposition (CVD) over the substrate (or pad film over the substrate), the trench side walls, and the underfill; then (ii) etching the dielectric over the pad film and the underfill, leaving a dielectric collar on the trench side walls.
When the process is performed in the second order recited above, the process may further comprise, between steps (a) and (b), the step of forming a barrier film over the substrate (or pad film over the substrate), the trench side walls, and the trench bottom. Such process may then further comprise, between steps (b) and (d), a step of removing the barrier film from the trench side walls in the upper region. Then, step (c) may comprise growing the collar by thermal oxidation.
Thus, the present invention may comprise the process of sequentially performing the steps of: (a) forming a pad film layer over a substrate; (b) forming a deep trench through the pad film layer and into the substrate; (c) filling the trench lower region with spin-on-glass underfill; (d) conformally depositing a dielectric material over the pad film, the trench side walls, and the spin-on-glass underfill; (e) etching the dielectric material over the pad film and the spin-on-glass underfill, leaving a collar of dielectric material on the trench side walls in the trench upper region; (f) removing the spin-on-glass underfill; and (g) forming a buried plate in the lower region.
The invention also may comprise the process of sequentially performing the steps of: (a) forming a pad film layer over a substrate; (b) forming a deep trench through the pad film layer and into the substrate; (c) forming a barrier film over the substrate, the trench side walls, and the trench bottom; (d) filling the trench lower region with spin-on-glass underfill; (e) etching the barrier film from the trench side walls in the upper region; (f) removing the spin-on-glass underfill; (g) thermally oxidizing the trench side walls in the upper region to grow a collar; and (h) forming a buried plate in the lower region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4782036 (1988-11-01), Becker et al.
patent: 5182224 (1993-01-01), Kim et al.
patent: 5200354 (1993-04-01), Om et al.
patent: 5352622 (1994-10-01), Chung
patent: 5482883 (1996-01-01), Rajeevakumar
patent: 5616961 (1997-04-01), Kohyama
patent: 5618751 (1997-04-01), Golden et al.
patent: 5656535 (1997-08-01), Ho et al.
patent: 5693568 (1997-12-01), Liu et al.
patent: 5710061 (1998-01-01), Cleeves
patent: 6057216 (2000-05-01), Economikos et al.
patent: 735581 (1996-10-01), None
patent: 791959 (1997-08-01), None
patent: 306061 (1901-06-01), None
IBM Technical Disclosure Bulletin vol. 27, No. 11, Apr. 1985.
Isolation Trench Filling by M. Arienzo and R.D. Isaac.
Gruening Ulrike
Radens Carl J.
Tobben Dirk
International Business Machines - Corporation
Perez-Ramos Vanessa
Ratner & Prestia
Utech Benjamin L.
LandOfFree
Process for manufacture of trench DRAM capacitor buried plates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacture of trench DRAM capacitor buried plates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacture of trench DRAM capacitor buried plates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2530075