Pipelined SAM register serial output

Details Pipelined SAM register serial output Pipelined SAM register serial output

1991-05-15

1994-06-28

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642448, 3642492, 3642514, 3642618, G06F 932

Patent

active

053255020

ABSTRACT:
Serial clock cycle time for a serial read operation in a semiconductor memory is reduced by partitioning the read operation into a sensing operation, a counter operation and an output operation, and conducting all three operations simultaneously in a pipelined fashion. To carry out the new method, the memory effectively is pipelined by providing a read register (92) between the sensing flip-flop (90) and the output latch/driver (96), and by isolating the address counter (48) from the address decoder circuitry (56) by inserting an isolation buffer (52). Additionally, the serial access time is reduced by conducting a look-ahead load (72) of a first tap address at the conclusion of a read transfer cycle, without waiting for the serial clock signal (SC) to begin the read cycle.

REFERENCES:
patent: 4891795 (1990-01-01), Pinkham et al.
patent: 5042014 (1991-08-01), Pinkham et al.
patent: 5097447 (1992-05-01), Ogawa et al.
patent: 5179372 (1993-01-01), West et al.
patent: 5198999 (1993-03-01), Abe et al.
patent: 5200925 (1993-04-01), Morooka
patent: 5206831 (1993-04-01), Wakamatsu

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