Multiplier having a reduced number of partial product calculatio

Details Multiplier having a reduced number of partial product calculatio Multiplier having a reduced number of partial product calculatio

1990-12-04

1992-06-02

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

051193256

ABSTRACT:
An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.

REFERENCES:
patent: 4745570 (1988-05-01), Diedrich et al.
patent: 4807175 (1989-02-01), Tokumaru et al.
patent: 4817029 (1989-03-01), Finegold
patent: 5008850 (1991-04-01), Jensen

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