Method to form selective cap layers on metal features with...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S638000, C438S672000, C438S700000

Reexamination Certificate

active

06893959

ABSTRACT:
Interconnect layers on a semiconductor device containing logic circuits (microprocessors, Asics of others) or random access memory cells (DRAM's) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of a selectively formed barrier layer on the recessed copper surfaces, is controlled to be essentially co-planar with the surrounding insulator surfaces. Because the barrier layers are recessed, shorting of adjacent conductive lines is prevented.

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