Method of reducing extrinsic base-collector capacitance in bipol

Details Method of reducing extrinsic base-collector capacitance in bipol Method of reducing extrinsic base-collector capacitance in bipol

1992-08-31

1994-03-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 7, 437126, 437133, 437909, 148DIG10, 148DIG72, H01L 21265

Patent

active

052984389

ABSTRACT:
This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

REFERENCES:
patent: 5024958 (1991-06-01), Awano
High-Performance AlGaAs/GaAs HBT's Utilizing Proton-Implanted Buried Layers and Highly Doped Base Layers, Osaake Nakajima, et al. IEEE Transactions on Electron Devices, vol. ED-34, No. 12, Dec. 1987, pp. 2393-2398.

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