Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-06-27
2006-06-27
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000
Reexamination Certificate
active
07067350
ABSTRACT:
Disclosed are techniques for constructing a novel solder bump layout on substrates for bonding using flip-chip, wafer-level, or other similar techniques. In one embodiment, a method of manufacturing a semiconductor device provides for forming contact pads on a first substrate, and forming an isolation layer over the contact pads and the substrate. In addition the method includes forming openings in the isolation layer over the contact pads, and depositing metal in the openings and in electrical contact with the contact pads to form electrical contacts in the openings. Also in such embodiments, the method includes bonding exposed surfaces of the electrical contacts to corresponding bonding pads formed on an external surface of a second substrate. In these embodiments, the bonding is done such that the isolation layer is in contact with the external surface to provide electrical isolation between the first and second substrates and between the electrical contacts.
REFERENCES:
patent: 5783870 (1998-07-01), Mostafazadeh et al.
patent: 6190940 (2001-02-01), DeFelice et al.
patent: 2002/0109228 (2002-08-01), Buchwalter et al.
Baker & McKenzie LLP
Cao Phat X.
Doan Theresa T.
Taiwan Semiconductor Manufacturing Company , Ltd.
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