Method of forming dual gate structure

Details Method of forming dual gate structure Method of forming dual gate structure

1998-12-30

2001-04-10

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000

Reexamination Certificate

active

06214671

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a gate of a semiconductor device, and more particularly, to a method of forming a dual gate.
2. Description of the Related Art
As semiconductor fabrication has reached the deep sub-micron stage, gates need to be formed with increasingly smaller dimensions, and with increasingly faster operation speed. The operation voltage is thus lowered, and consequently a change in material and fabrication must be made to avoid any device instability.
Conventionally, in either an N-channel metal-oxide semiconductor (NMOS) or a P-channel metal-oxide semiconductor (PMOS), a gate is formed of a polysilicon layer doped with N-type ions. A tungsten silicide layer and a silicon nitride layer are then formed on the gate. While forming a PMOS, an ion implantation is performed to an N-well or an N-type substrate for adjusting the threshold voltage of the PMOS. As a consequence, a PN junction is formed to induce a depletion region. The induced depletion region induces an equivalent buried channel device that causes a short channel effect, so that problems arise, such as sub-threshold voltage and an inability of the gate to control the device.
Due to the above problems, a method of doping P-type ions into a polysilicon gate of a PMOS has been developed. Thus, a complementary MOS (CMOS) comprising two gates doped with different conductive types has been formed and has become a leading trend for further development of gate fabrication. For example, embedded dynamic random access memory (Embedded DRAM) employs this type of gate.
FIG. 1A
to
FIG. 1D
show a conventional method of fabricating a dual gate. In
FIG. 1A
, a substrate
100
is provided. Using ion implantation, an N-well
101
and a P-well
102
are formed in the substrate
100
. A shallow trench isolation
103
is formed between the N-well
101
and P-well
102
for isolation. A gate oxide layer
104
is formed on the substrate
100
. A polysilicon layer
105
is formed on the gate oxide layer
104
. The part of the polysilicon layer
105
over the P-well
102
is covered by a photoresist layer
106
, while the other part polysilicon layer
105
over the N-well
101
is exposed. N-type ions are implanted into the exposed part of the polysilicon layer
105
.
In
FIG. 1B
, the photoresist layer
106
is removed. Another photoresist layer
107
is formed to cover the part of the polysilicon layer
105
over the N-well
101
, and the polysilicon layer
105
over the P-well
102
is exposed. P-type ions are implanted into the exposed part of the polysilicon layer
105
.
In
FIG. 1C
, the photoresist layer
107
is removed. A high temperature diffusion is performed to define the N-type polysilicon layer
105
a
on the N-well
101
and the P-type polysilicon layer
105
b
on the P-well
102
. A part of the N-type polysilicon layer
105
a
and a part of the P-type polysilicon layer
105
b
are removed to form an N-type gate
105
a
on the N-well
101
and a P-type gate
105
b
on the P-well
102
. Spacers
109
are formed on the sidewalls of the N-type gate
105
a
and on the P-type gate
105
b
. Source/drain regions
111
a
and
111
b
are formed in the in the substrate beside the N-type gate
105
a
and the P-type gate
105
b
, respectively.
In
FIG. 1D
, a titanium layer (not shown) is formed on the N-type gate
105
a
and the P-type gate
105
b
. A thermal process is performed to form self-aligned silicide on the N-type gate
105
a
, the P-type gate
105
b
and the source/drain regions
111
a
,
111
b
. The remaining titanium layer is removed.
Since the silicide
113
is formed from titanium and doped polysilicon, the silicide
113
has a high resistance. To decrease the resistance of the silicide, dopant concentration in the polysilicon is limited. However, a doping concentration of the N-type polysilicon and a doping concentration of the P-type polysilicon are lower, and the area of a depletion region between the P-type polysilicon and the N-type polysilicon is larger.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of forming a dual gate structure to form silicide with a low resistance on a gate and a source/drain region by self-alignment.
It is another object of the invention to provide a method of forming a dual gate structure. The dual gate structure comprises an N-type gate and a P-type gate. A depletion region between the N-type gate and the P-type gate is smaller than a convention dual gate structure.
The invention achieves the above-identified objects by providing a method of forming a dual gate structure. A substrate is provided. A first well with a first conductive type and a second well with a second conductive type are formed in the substrate. An isolation structure is formed between the first well and the second well. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. A part of the polysilicon layer positioned on the first well is doped to become a first-type polysilicon layer. Another part of the polysilicon layer positioned on the second well is doped to become a second-type polysilicon layer. An undoped polysilicon layer is formed on the doped polysilicon layer. A part of the undoped polysilicon and a part of the doped polysilicon layer are removed to form a first gate on the first well and a second gate on the second well. Spacers are formed on the sidewalls of the first gate and on the second gate. Source/drain regions are formed in the substrate beside the first gate and the The exposed portions of oxide layer beside the gate structures are removed. second gate. Silicide is formed on the first gate, the second gate and the source/drain regions by self-alignment to form a dual gate structure comprising the first gate and the second gate.
The gate formed according to the invention comprises a silicide layer. The silicide layer is formed from a metal layer reacting with the undoped polysilicon layer so that the silicide layer has a lower resistance than a conventional silicide layer. Furthermore, the doped polysilicon layer is not used to form the silicide layer. Dopant concentration of the doped polysilicon layer does not affect the resistance of the silicide layer. The dopant concentration can be increased to reduce the depletion region between the P-type gate and the N-type gate.


REFERENCES:
patent: 5512502 (1996-04-01), Oostuka et al.
patent: 5840607 (1998-11-01), Yeh et al.
patent: 5877523 (1999-03-01), Liang et al.
patent: 5943592 (1999-08-01), Tsukamoto et al.
patent: 5977561 (1999-11-01), Wu
patent: 5998290 (1999-12-01), Wu et al.

Affiliated with

Also associated with

Rating

Method of forming dual gate structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming dual gate structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming dual gate structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2456497