Method for manufacturing silicon carbide MOS semiconductor...

Details Method for manufacturing silicon carbide MOS semiconductor... Method for manufacturing silicon carbide MOS semiconductor...

1999-06-30

2001-05-29

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S269000, C438S285000, C438S306000

Reexamination Certificate

active

06238980

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing silicon carbide MOS semiconductor devices, such as MOS field-effect transistors (hereinafter referred to as “MOSFET”), having a MOS type gate of metal-oxide-semiconductor structure, which use silicon carbide as a semiconductor material and serve as power semiconductor devices. The invention also relates to such silicon carbide MOS semiconductor devices.
BACKGROUND OF THE INVENTION
Silicon carbide (hereinafter referred to as “SiC”) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon (hereinafter referred to as “Si”) by one order of magnitude. Thus, SiC has been highly expected to be used as a material for power semiconductor devices in the next generation. Up to the present, various types of electron devices, in particular, those for switching large power at high temperatures, have been developed, using single-crystal wafers, such as 4H—SiC and 6H—SiC. These crystals are alpha-phase SiC in which a zinc-blend structure and a wurtzite structure are superposed on each other. Also, some semiconductor devices have been fabricated using crystals of beta-phase SiC, such as 3C—SiC. Recently, power devices, such as Schottky diodes, vertical MOSFET, and thyristors, and CMOS-IC as the most typical semiconductor devices, have been fabricated using SiC as a semiconductor material, and it has been confirmed that these devices exhibit far better characteristics than conventional Si semiconductor devices.
The present invention relates to a MOS semiconductor device having a MOS type gate. Some examples of known Si MOSFET and SiC MOSFET will be now described.
FIG. 4
is a cross-sectional view of a unit cell of typical Si vertical MOSFET that has been generally used as a power semiconductor device. In the Si vertical MOSFET of
FIG. 4
, an n drift layer
11
b
having a high resistivity is laminated on an n
+
drain layer
11
a
, and a p base region
12
is formed in a selected area of a surface layer of the n drift layer
11
b,
while an n
+
source region
13
is formed within the p base region
12
. A gate electrode layer
16
made of polycrystalline silicon or polysilicon is formed on a gate insulating film
15
, over the surface of the p base region
12
interposed between the n
+
source region
13
and an exposed surface portion of the n drift layer
11
b.
A source electrode
17
is formed in contact with surfaces of both of the n
+
source region
13
and p base region
12
, and a drain electrode
18
is formed on the n
+
drain layer
11
a
on the rear surface of the n drift layer
11
b.
As shown in
FIG. 4
, the source electrode
17
is often extended over the gate electrode layer
16
via an interlayer insulating film
19
. A gate electrode made of metal is held in contact with the gate electrode layer
16
at a portion that is not illustrated in the figure.
In the operation of the vertical MOSFET as described above, when a positive voltage is applied to the gate electrode, an inversion layer appears in a channel region
20
, namely, a surface layer of the p base region
12
located right under the gate electrode layer
16
, so that current flows between the source electrode
17
and the drain electrode
18
through the inversion layer. If the positive voltage stops being applied to the gate electrode, the inversion layer of the channel region
20
disappears, and the current stops flowing through the channel region
20
.
Thus, the channel region
20
plays an important role in the above operation, and its length is desired to be strictly or accurately controlled. To this end, a method called diffusion self alignment (that may be abbreviated to DSA) is employed in the manufacture of Si MOSFET, and the resulting MOSFET may be called double diffusion MOSFET.
Main process steps for manufacturing the double diffusion MOSFET will be now described, referring to the cross-sectional views of FIG.
5
(
a
) through FIG.
5
(
f
) showing the respective steps.
In the step of FIG.
5
(
a
), an n drift layer
11
b
having a high resistivity is laminated on an n
+
drain layer
11
a
by epitaxial growth, to provide a Si wafer, which is then subjected to thermal oxidation so that a gate oxide film
15
is formed on the n drift layer
11
b.
Thereafter, a polysilicon film
1
is deposited on the gate oxide film
15
by low-pressure CVD method.
In the next step of FIG.
5
(
b
), the polysilicon film
1
is patterned by photolithography, to thus form a gate electrode layer
16
, and boron ions
2
a
, or the like, for forming a p base region
12
are implanted, using the gate electrode layer
16
as a mask. In FIG.
5
(
b
), reference numeral
2
b
denotes boron atoms thus implanted. Thereafter, heat treatment is conducted so as to form the p base region
12
, as shown in FIG.
5
(
c
).
In the next step of FIG.
5
(
d
), arsenic ions
3
a
, for example, for forming an n
+
source region
13
are implanted, using the gate electrode layer
16
and a photoresist
7
as masks. In FIG.
5
(
c
), reference numeral
3
b
denotes arsenic atoms thus implanted. Thereafter, heat treatment is conducted again, so as to form the n
+
source region
13
, as shown in FIG.
5
(
e
).
In the next step of FIG.
5
(
f
), boron/phosphorous/silica glass (BPSG) is deposited on the structure by plasma CVD method, to provide an interlayer insulating film
19
, and a window or hole is formed through the insulating film
19
by photolithography. A metal that provides an electrode is deposited on the Si substrate, and patterned so as to form a source electrode
17
and others, as shown in FIG.
5
(
f
). Thereafter, a drain electrode (not illustrated) is formed on the rear surface of the Si substrate, and the manufacturing process is completed.
While a high-concentration p
+
well region that overlaps the p base region
12
may be provided in the structure of
FIG. 5
, such a p
+
well region can be formed by implanting impurity ions using the gate electrode layer
16
and photoresist as used for forming the n
+
source region
13
, and then conducting heat treatment.
What is important in the above process is that the polysilicon film
1
that provides the gate electrode layer
16
is used as a mask during ion implantation for forming the p base region
12
and the n
+
source region
13
. Since the p base region
12
and n
+
source region
13
use the same mask, there arises no variations in the position of the mask, and the dimensions of the channel region
20
formed in a portion of the p base region
12
right below the gate electrode layer
16
are accurately and uniformly controlled due to lateral diffusion of impurities during formation of the p base region
12
and n
+
source region
13
.
The channel dimensions that influence the characteristics of the MOSFET can be controlled with high accuracy by introducing p type impurities and n type impurities into selected regions using the same mask, and causing thermal diffusion. Thus, the diffusion self alignment method (DSA method) makes it possible to produce high performance MOSFET with a high yield.
On the other hand, SiC is a semiconductor material that is highly expected to be applied to power devices in the future, and its important applications include vertical MOSFET. For example, trench type or planar type vertical MOSFETs have been fabricated using SiC.
FIG. 6
is a cross-sectional view showing a part of a unit cell of SiC vertical UMOSFET as one example of MOSFET (as disclosed in Weitzel, C. W. et al.: IEEE Trans. on Electron Devices, vol. 43, No. 10, pp. 1732-1741 (1996), Agarwal, A. K. et al: Abstract of Int. Conf. Silicon Carbide, III-nitrides and Related Materials (1997) pp. 156-157).
In the SiC vertical UMOSFET, an n drift layer
21
b
and a p base layer
22
are laminated on an n
+
drain layer
21
a
, and an n
+
source region
23
is formed in a surface layer of the p base layer
22
. A trench
8
that extends from the surface of the n
+
source region
2

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