Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-25
2001-12-25
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06333231
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor read-only memory, such as a mask ROM, and a method for conserving a semiconductor wafer from which to make the above-mentioned memory.
2. Description of the Related Art
A conventional mask ROM, in which one memory cell includes an insulated gate transistor such as a MOS transistor, is generally manufactured in steps as follows:
(1) Step (a)
A gate oxide film for a MOS transistor is formed on a p-type silicon substrate.
(2) Step (b)
A gate electrode layer is formed by depositing a polysilicon film on the wholesale surface of the above-mentioned oxide film and diffusing impurities into the polysilicon film to impart electric conductivity to it.
(3) Step (c)
The gate electrode layer is patterned by photolithography to form gate electrodes of the MOS transistors as the insulated gate transistors used in the memory cells.
(4) Step (d)
Prior to the implantation of phosphorus ions into the surface of the silicon substrate on which the gate electrode has been formed, an oxide film is formed to protect the substrate surface from ion implantation.
(5) Step (e)
For the source and drain regions consisting of doped regions to be formed on both sides of the gate electrode, phosphorus ions are implanted in the regions on both sides of the gate electrode through the protective oxide film. Thereafter, the phosphorus ions implanted in the oxide film are diffused in the silicon substrate by heat treatment. By this thermal diffusion, the source and drain regions are formed which correspond to the source and drain electrodes of a MOS transistor.
(6) Step (f)
By chemical vapor deposition (CVD), an inter-layer dielectric film of silicon dioxide is formed on the above-mentioned oxide film of the silicon substrate at a substrate temperature of about 400° C. The inter-layer dielectric film can be grown by CVD at lower temperatures than in thermal oxidation widely used to obtain silicon dioxide by heating silicon, and this dielectric film is superior in terms of freedom from inadvertent thermal diffusion of the impurities in the source and drain regions.
(7) Step (g)
A photoresist film is formed on the above-mentioned inter-layer dielectric film. After this, by using a memory pattern based on data to be written on a ROM, the photoresist film is selectively exposed to light and developed, a resist pattern corresponding to the ROM data is formed. By using this resist pattern, ions are implanted below the gate electrodes of the memory cells selected to change the threshold voltages of the MOS transistors. By selective ion implantation described above, data is written in the ROM transistors.
(8) Step (h)
After the resist pattern is removed, metal lines of aluminum, for example, are formed on the gate electrode, source and drain of the MOS transistor.
After this, a passivation film is formed to protect the surfaces of the MOS transistors and their wiring patterns, and then the semiconductor wafer on which many memory cells have been formed undergoes inspection. After inspection, the wafer is cut into individual memory chips. Each memory chip is mounted on a substrate for a package, and the memory chip is provided with external leads and packaged. Thus, a memory device is completed.
Meanwhile, the conventional method for manufacturing a mask ROM mentioned above has a problem as follows.
Efforts are being made to reduce the required turn-around time (hereafter referred to merely as TAT) from the stage of design when the memory contents of a mask ROM are decided till the product is completed. A possible solution is to store semiconductor wafers that have passed the above-mentioned Steps up to (f) and after the memory contents have been decided, start the successive manufacturing steps (g) and (h) mentioned above.
However, if the storage period of the wafers stretches to a long period of six months or so, semiconductor wafers that have undergone Step (f) and have been covered with an interlayer dielectric film consisting of porous silicon dioxide formed by CVD, will absorb moisture in the air, potentially resulting in the above-mentioned inter-layer dielectric film decreasing in insulating performance.
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor memory capable of having semi-finished wafers kept in storage for longer periods than found in the prior art and also capable of reducing the TAT.
Another object of the present invention is to provide a method of safekeeping semiconductor wafers for semiconductor memories for longer periods than found in the prior art.
SUMMARY OF THE INVENTION
To achieve the one object, according to the present invention, there is provided a method for manufacturing a semiconductor read-only memory on which data has been written, comprising the steps of forming on a semiconductor substrate a plurality of memory cells for storing data, each consisting of an insulated gate transistor having a gate electrode; forming on the semiconductor substrate by chemical vapor deposition a dielectric film to bury therein the insulated gate transistors formed on the semiconductor substrate; performing thermal processing on the substrate to reduce the water content of the dielectric film; and writing data by implanting ions into the memory cells selected to bias a threshold voltage of the transistors of the memory cells selected corresponding to data to be written.
In the above manufacturing method, the thermal processing may be performed in an inert gas atmosphere.
Heating lamps may be used as heat sources in the thermal processing.
A silicon substrate may be used for the semiconductor substrate.
In the ion implantation to the memory cells selected, a mask may be used to permit ions to be implanted into the semiconductor substrate below the gate electrode while passing by the gate electrodes of the transistors selected.
The temperature of the thermal processing may be lower than the melting point of a material for the gate electrode.
The dielectric film may be a silicon dioxide film and the silicon dioxide film may be formed by atmospheric pressure CVD at 600° C. or below.
The thermal processing may be performed under conditions of a temperature range of 700° C. to 800° C. for 60 seconds or less in a nitrogen gas atmosphere.
Metal wiring may be formed for the memory cells on the dielectric film, and after said metal wiring is formed, the thermal processing may be formed on the substrate at a temperature lower than the melting point of the metal wiring.
To achieve the other object, there is provided a method for storing semiconductor wafers for manufacture of read-only memory in which data has been written, comprising the steps of:
forming a plurality of memory cells for storing data on a semiconductor substrate made of a semiconductor wafers;
forming a dielectric film on the semiconductor substrate to blanket the memory cells;
performing thermal processing on the substrate to reduce the water content of the dielectric film; and
storing the semiconductor substrate after receiving the thermal processing until data is written in the memory cells.
The semiconductor substrate may be stored under the condition that a water-proofing film to prevent entry of moisture into the dielectric film is formed on the surface of the heat-treated dielectric film.
In the storage method, the waterproofing film may be formed by a barrier metal.
REFERENCES:
patent: 4129936 (1978-12-01), Takei
patent: 4364167 (1982-12-01), Donley
patent: 5264724 (1993-11-01), Brown et al.
patent: 5736420 (1998-04-01), Min et al.
patent: 6177350 (2001-01-01), Sundarrajan et al.
patent: 6190926 (2001-02-01), Perino et al.
Seto Masaru
Takahashi Hiroaki
Elms Richard
Frank Robert J.
OKI Electric Industry Co., Ltd.
Owens Beth E.
Venable
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