Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-19
2002-12-31
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S247000, C438S246000, C438S245000, C438S244000, C438S243000, C438S392000, C438S390000, C438S389000, C438S388000, C438S387000, C438S386000
Reexamination Certificate
active
06500707
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor and memory technology fields. More specifically, the invention pertains to a method for manufacturing a trench capacitor that can be a component of a memory cell of a semiconductor memory.
Semiconductor memories, such as for example DRAMs (Dynamic Random Access Memories), are made up of a cell field and peripheral drive control equipment. Individual memory cells are situated in the cell field.
A DRAM chip contains a matrix of memory cells that are arranged in the form of rows and columns, and are controlled by word lines and bit lines. The reading out of data from the memory cells, or the writing of data to the memory cells, is accomplished through the activation of suitable word lines and bit lines.
Conventionally, a memory cell of a DRAM contains a transistor that is connected with a capacitor. Among other things, the transistor is made up of two diffusion regions that are separated from one another by a channel that is controlled by a gate. One diffusion region is called the drain region, and the other diffusion region is called the source region.
One of the diffusion regions is connected with a bit line, the other diffusion region is connected with a capacitor, and the gate is connected with a word line. Through application of suitable voltages to the gate, the transistor is controlled in such a way that a flow of current between the diffusion regions through the channel is switched on and switched off.
Due to the progressive miniaturization of memory components, the integration density is continually being increased. The continual increasing of the integration density means that the surface available per memory cell is constantly decreasing. This has the result that the selection transistor and the storage capacitor of a memory cell are subjected to a constant reduction in their geometrical dimensions.
The continuing effort towards miniaturization of memory devices promotes the design of DRAMs having greater density and smaller characteristic size, i.e., smaller memory cell surface. In order to manufacture memory cells that require a smaller surface area, smaller components, such as for example capacitors, are used. However, the use of smaller capacitors results in a lower storage capacity of the individual capacitor, which in turn can have an adverse effect on the functional capability and applicability of the memory device. For example, read amplifiers require a sufficient signal level for the reliable reading out of the information stored in the memory cells. The ratio of storage capacity to bit line capacity is decisive in the determination of the signal level. If the storage capacity becomes too small, this ratio can be too small to produce a sufficient signal for the controlling of the read amplifier. Likewise, a smaller storage capacity requires a higher refresh frequency. An additional disadvantage of a capacitor that has been reduced in its geometrical dimensions is to be found in the electrical supply lines, which are likewise fashioned with a reduced cross-section, through which the resistance of the supply lines is increased and the speed of the individual memory cell is reduced.
According to U.S. Pat. No. 5,744,386 it is known to produce a selective epitaxial layer on an exposed lateral wall in trench capacitors for the formation of a vertical selection transistor.
According to U.S. Pat. No. 6,066,527, it is known, for example, to produce an insulating collar in an upper region of a trench.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of fabricating a trench capacitor of a memory cell of a semiconductor memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for lower manufacturing costs and increased capacitance of the trench capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of manufacturing a trench capacitor, which comprises the following method steps:
providing a substrate with a substrate surface;
forming a trench with an upper region, a lower region, and a side wall in the substrate, the upper region being closer to the substrate surface than the lower region;
isotropically etching the trench to widen the trench in the upper region and the lower region;
conformally depositing a first insulating layer in the trench;
etching the first insulating layer with directed etching to form the first insulating layer as a lateral edge web;
removing the first insulating layer from the lower region of the trench, thereby forming an insulating collar in the upper region from the first insulating layer, the collar extending into the trench from the substrate surface down to a first sinking depth;
forming a capacitor dielectric on the substrate in the lower region of the trench and on the insulating collar in the upper region of the trench;
filling the trench with a conductive trench filling;
sinking the insulating collar into the trench down to a second sinking depth located between the substrate surface and the first sinking depth, and exposing the substrate on the side wall of the trench, above the second sinking depth;
sinking the conductive trench filling and the capacitor dielectric into the trench down to a third sinking depth located between the first sinking depth and the second sinking depth;
selective-epitaxially growing a selective epitaxial layer on the exposed side wall of the trench; and
forming an electrical contact between the conductive trench filling and a doping region of a selection transistor. With the novel process there is formed a trench capacitor having a buried insulating collar and an epitaxial layer is formed, which is grown above the insulating collar in the trench, starting at the substrate. The buried insulating collar has the advantage that the trench capacitor is formed with a larger diameter than is provided by the lithographic mask used for its structuring. In this way, the trench capacitor is formed with a larger cross-sectional surface, which on the one hand enables a larger surface of the electrodes of the trench capacitor, through which the capacitance of the trench capacitor is increased, and on the other hand enables a larger cross-sectional surface for the conductive trench filling that forms the inner capacitor electrode of the trench capacitor and forms an electrical connection between the inner capacitor electrode B through the insulating sleeve formed by the insulating collar B to a doping region of a selection transistor. Through the enlarged cross-sectional surface of the conductive trench filling in the tubular insulating jacket formed by the insulating collar, a reduced electrical resistance is enabled, through which the time required for reading out and for storing an item of information in the trench capacitor can be reduced. The inventive combination of the buried insulating collar with a selective epitaxial layer grown above the insulating collar in the trench makes it possible to form the selection transistor of the memory cell closer to the trench capacitor, thus reducing the overall surface claimed by the memory cell. In this way, leakage currents between adjacent contact regions are likewise reduced.
An advantageous construction of the inventive method provides that a masking layer is situated on the substrate surface, and the directed etching of the first insulating layer is carried out selectively to the masking layer with etching gas containing carbon fluoride, such as C
4
F
8
, C
5
F
8
, or C
2
F
6
. Through the described etching with the named etching gases, the first insulating layer is formed in the trench as a lateral edge web. Because a widening of the trench was previously carried out, the masking layer blocks or screens the side wall of the trench, so that the insulating layer remains on the side wall of the trench during the directed etching.
A further construction of the inventive method provides that with the fir
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