Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-10-31
2006-10-31
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S643000, C438S687000
Reexamination Certificate
active
07129165
ABSTRACT:
A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.
REFERENCES:
patent: 6297154 (2001-10-01), Gross et al.
patent: 6342447 (2002-01-01), Hoshino
patent: 6524950 (2003-02-01), Lin
patent: 6720248 (2004-04-01), Ryo
Shannon et al., “Copper Interconnects for High-Volume Manufacturing,”Semiconductor International, Novellus Systems Inc., San Jose, CA, May 1, 2001.
Basol Bulent M.
Talieh Homayoun
ASM Nutool, Inc.
Knobbe Martens Olson & Bear LLP
Vu Hung
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