Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-17
2001-11-20
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S678000
Reexamination Certificate
active
06319834
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for forming a layer of electrically conductive material filling a plurality of spaced apart recessed areas of different widths and depths formed in the surface of a substrate, wherein the exposed upper surface of the layer is substantially coplanar with the non-recessed areas of the substrate surface. More particularly, the invention relates to a method for “back-end” metallization of semiconductor integrated circuit devices which facilitates planarization by chemical-mechanical polishing (CMP), increases manufacturing throughput, and improves product quality.
BACKGROUND OF THE INVENTION
This invention relates to a method and apparatus for forming metal films as part of metallization processing of particular utility in integrated circuit semiconductor device and circuit board manufacture, which processing employs “damascene” (or “in-laid”) technology.
Metal films of the type contemplated herein are used, e.g., in “back-end” semiconductor manufacturing technology, to form electrically conductive contacts to active as well as passive device regions or components formed in or on a semiconductor substrate, as well as for filling via holes, interlevel metallization, and interconnection routing patterns for wiring together the components and/or regions. Metals employed for such purposes include titanium, tantalum, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. Of these, copper and copper-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large scale integration (ULSI) devices requiring multilevel metallization systems for “back-end” processing of the semiconductor wafers on which the devices are based. Copper and copper-based metallization systems have very low resistivities, i.e., even lower than those of previously preferred systems utilizing aluminum and its alloys, as well as significantly higher resistance to electromigration. Moreover, copper and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to aluminum and refractory-type metals, copper and its alloys can be readily deposited in good quality, bright layer form by well known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
Referring now to
FIG. 1
, schematically shown therein in cross-sectional view is a conventional damascene processing sequence for forming recessed metallization patterns (i.e., “back-end” contacts, vias, interconnections, routing, etc.) in a semiconductor device formed in or on a semiconductor wafer substrate
1
. In a first step, the desired conductor pattern is defined as a pattern of recesses
2
such as grooves, trenches, holes, etc., formed (e.g., by etching) in the surface
4
of a dielectric layer
3
deposited or otherwise formed over the semiconductor substrate, followed by a second step comprising deposition of a suitably conductive metal layer
5
filling the etched recesses
2
. Typically, in order to ensure complete filling of the recesses, the metal layer
5
is deposited as a blanket (or “overburden”) layer of excess thickness t so as to overfill the recesses
2
and cover the upper surface
4
of the dielectric layer
3
. Next, the entire excess thickness t of the metal overburden layer
5
over the surface
4
of the dielectric layer
3
is removed using a chemical-mechanical polishing (CMP) process, leaving metal portions
5
′ in the recesses
2
with their exposed upper surfaces
6
substantially coplanar with the surface
4
of the dielectric layer
3
. Thus this conventional process, termed “damascene process”, forms in-laid conductors
5
′ in the dielectric layer
3
while avoiding problems associated with other types of processes, e.g., metal etching and dielectric gap filling.
While such damascene processing can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, with a plurality of metallization levels (e.g., five or more levels), and with any of the previously enumerated metals, the parallel drives toward cost reduction and increased microminiaturization of semiconductor devices have provided impetus for greater utilization of copper or copper-based metallization/interconnection metallurgy, particularly in view of the above-described advantages obtainable thereby. However, the use of copper-based metallurgy has presented several problems, including the possibility of copper diffusion into the silicon semiconductor substrate and poor adhesion to various dielectric materials, necessitating provision of an adhesion promoting and/or diffusion barrier layer (e.g., chromium, tantalum, or tantalum nitride) prior to deposition of copper-based metallization.
Another problem associated with damascene processing of copper-based interconnection metallurgy arises from the use of electrolytic deposition of the copper material filling recesses of various geometrical shapes, widths, and depths, and for forming the overburden layer subsequently removed by CMP processing. While electroplating has advantages, such as rapid deposition rates vis-à-vis those obtainable by “dry” processes such as physical or chemical vapor deposition and good compatibility with “wet” CMP processing, electrolytic deposition of copper-based metallization layers suffers from the drawback of ridge build-up and non-planarity at sharp corners of vias, grooves, and trenches.
Referring now to
FIG. 2
, wherein like reference numerals are used to designate similar features in
FIG. 1
, in typical practice, a semiconductor wafer substrate
1
will include a variety of recesses
2
of different cross-sectional shapes, widths, and/or depths formed in overlying dielectric layer
3
, depending upon the particular metallization feature to be formed. In the illustrated embodiment, recess
2
′ extends entirely through the thickness of dielectric layer
3
for establishing ohmic contact to active device or component region
7
formed in or on substrate
1
, and recesses
2
″ and
2
′″ extending to similar depths within the dielectric layer
3
are respectively of narrow and wide widths.
In conventional electroplating processing of structures such as those illustrated in
FIG. 2
, the wafer is immersed in an electrolyte bath containing copper and subjected to electroplating for simultaneously filing the recesses
2
′,
2
″,
2
′″ and forming a rather thick blanket or overburden layer
5
of copper, of thickness t
1
from about 0.5 &mgr;m to about 1.5 &mgr;m, to ensure complete filling of the deepest resess(es), e.g., recess
2
′, and for accommodating the different deposition material requirements of the other recesses of various shapes and dimensions, e.g.,
2
″ and
2
′″. The resulting overburden layer
5
has generally the same thickness t
1
in the relatively wide recess(es)
2
′″ as over the non-recessed portions
4
of the surface. As a consequence, the exposed upper surface of the overburden layer
5
is highly non-planar due to the formation of ridges and valleys, such as shown in
8
. In addition, dimples
8
′ are formed in layer
5
at deep recess(es)
2
′.
Removal of such thick, non-planar overburden layers
5
of copper in the subsequent CMP step for planarizing the interconnection metallization pattern entails a number of drawbacks. First, CMP of copper or copper-based alloys is slow and expensive. Specifically, typical copper removal rates by CMP employing a conventional alumina-based slurry are on the order of about 2,000-3,000 Å/min. Consequently, removal of 0.5 -1.5 &mgr;m thick copper layers can require long processing times extending up to about 5 minutes, considerably longer than that desired for good manufacturing throughput and reduced expense. Second, because a hard
Avanzino Steven C.
Erb Darrell M.
Wang Fei
Advanced Micro Devices , Inc.
Tsai Jey
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