Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-03
2002-12-31
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S660000, C438S688000
Reexamination Certificate
active
06500757
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to conductive stacks for interconnects and methods of manufacturing conductive stacks. More particularly, the present invention relates to a conductive stack, such as a metal stack, resistant to grain growth roughening.
BACKGROUND OF THE INVENTION
Device sizes and geometries associated with integrated circuits have become increasingly smaller. Smaller device sizes and geometries allow integrated circuits to achieve greater densities, faster speeds, and lower power consumption. Reducing device sizes and geometries necessitates the use of more precisely dimensioned circuit interconnects. Circuit interconnects or conductive lines are generally utilized to connect semiconductive or conductive structures within the integrated circuit. Presently, interconnects for integrated circuits include multiple layers to create conductive (e.g., metal) stacks.
A conductive stack (e.g., a metal one layer, a metal two layer, a metal three layer, or a metal four layer) including aluminum (Al) or aluminum alloys, also referred to as an aluminum stack, is generally comprised of an aluminum metallization layer sandwiched between conductive underlayers and overlayers. Conductive underlayers include a titanium (Ti) underlayer and a titanium nitride (TiN) underlayer. Conductive overlayers include a titanium (Ti) overlayer and a titanium nitride (TiN) overlayer. The aluminum metallization layer includes aluminum material doped with copper (Cu). The TiN underlayer is disposed over the Ti underlayer, and the aluminum metallization layer (e.g., aluminum line) is disposed over the TiN underlayer. The Ti overlayer is disposed over the aluminum metallization layer, and the TiN overlayer is disposed over the Ti overlayer. This conductive stack is then masked and etched to form a plurality of interconnects, each interconnect configured to be an electrically isolated aluminum line for carrying a unique current.
In conventional conductive stack fabrication, it is extremely difficult to achieve perfect grain structure or crystallographic texture of the aluminum alloy deposited to form the aluminum metallization layer. Generally, the aluminum metallization layer will include various crystalline imperfections or defects such as grain boundaries. Grain boundaries make the aluminum lines more susceptible to electromigration.
To reduce the electromigration problem, conductive underlayers, such as the Ti and TiN underlayers, and copper doping of aluminum are implemented. The conductive underlayers reduce electromigration by improving the grain structure and grain size, i.e., the crystalline structure, of the aluminum metallization layer such that less grain boundaries are formed. The copper doping of aluminum reduces electromigration when copper undergoes theta (&thgr;) phase precipitation to form CuAl
2
, a sub-stoichiometric alloy, along the grain boundaries instead of being uniformly distributed throughout the aluminum alloy. These copper precipitates retard grain boundary diffusion, thereby decreasing total mass transport to reduce electromigration.
Although copper precipitates can reduce electromigration, it can also cause micromasking, leading to uneven etching and even shorting of two or more aluminum lines. Aluminum alloys with copper levels above one percent in weight are difficult to etch. The etch chemistry used to etch aluminum alloys essentially cannot etch pure copper or even a high concentration (e.g., two percent) of copper (such as is found at the grain boundaries). Thus, when the aluminum alloy is being etched, high copper concentration sites are seen as micromasks such that nothing will be etched below it or will only partially etch below it. Undesirable residues at the high copper concentration sites can make the etched surface rough. Furthermore, these residues can inadvertently bridge two or more aluminum lines causing interconnects to short circuit (e.g., be inadvertently connected).
Thus, there is a need for an integrated circuit including a conductive stack that is resistant to grain growth induced roughening and micromasking. Further still, there is a need for a method of manufacturing a conductive stack that is resistant to grain growth induced roughening and micromasking. Even further still, there is a need for an aluminum line interconnect that is resistant to copper precipitation and lithography problems associated therewith.
SUMMARY OF THE INVENTION
One exemplary embodiment relates to an integrated circuit including a conductive stack. The conductive stack includes an interconnect metallization layer comprising an aluminum-copper alloy, wherein the interconnect metallization layer is formed at a low diffusivity temperature of the aluminum-copper alloy to minimize undesirable copper precipitation.
Another exemplary embodiment relates to an integrated circuit. The integrated circuit includes a device, an interlevel dielectric layer, and a conductive stack. The interlevel dielectric layer is disposed over the device and the conductive stack is disposed over the interlevel dielectric layer to form an interconnect line of the device. The conductive stack is partially formed at a processing temperature less than 200° C. to provide resistance to grain growth induced roughening and interconnect line bridging.
Still another exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing an interconnect metallization layer over an interlevel dielectric layer at a low diffusivity temperature to form a conductive stack. The method further includes providing an overlayer over the interconnect metallization layer at the low diffusivity temperature to further form the conductive stack. The method still further includes processing the conductive stack after providing an overlayer step at the low diffusivity temperature when the interconnect metallization layer would otherwise be thermally affected, to minimize residue formation.
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Morales Guarionex
Shields Jeffrey A.
Advanced Micro Devices , Inc.
Foley & Lardner
Quach T. N.
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