Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-03-15
2000-07-18
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438634, 438637, H01L 214763
Patent
active
060907002
ABSTRACT:
A metallization method for forming contact studs and via plugs is disclosed. The method includes: patterning first conductive contacts over a substrate; forming a first dielectric layer over the first conductive contacts and the substrate; forming a sacrificial layer on the first dielectric layer; forming openings through portions of the sacrificial layer and the first dielectric layer until the first conductive contacts are exposed; filling the openings with a second conductive layer; etching back the second conductive layer until the surfaces of the second conductive layer in the openings are near the interface of the sacrificial layer and the first dielectric layer; and removing the sacrificial layer. A metallization method for a multi-level conductive system is also disclosed.
REFERENCES:
patent: Re34583 (1994-04-01), Grief et al.
patent: 4879257 (1989-11-01), Patrick
patent: 5210053 (1993-05-01), Yamagata
patent: 5286675 (1994-02-01), Chen et al.
patent: 5591673 (1997-01-01), Chao et al.
Silicon Processing for the VLSI Era, vol. 1: Process Technology, Stanley Wolf Ph.D., Richard N. Tauber Ph.D., Lattice Press, 1986, pp. 365-374.
Everhart Caridad
Vanguard International Semiconductor Corporation
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