Binary logic level electrical detector namely to prevent the det

Details Binary logic level electrical detector namely to prevent the det Binary logic level electrical detector namely to prevent the det

1988-06-29

1990-04-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072964, 307362, 307530, 307585, 365196, 361172, 361171, 34082531, 34082532, G06F 704, G06K 500, G06K 701, H03K 1730

Patent

active

049163337

ABSTRACT:
To prevent fraudulent action by ill-intentioned users, the detection of the secret codes, contained in a memory card with MOS integrated circuit and transmitted to an input/output unit, is prevented. This is done by interposing a read amplifier in the transmission chain, in the integrated circuit itself. This read amplifier essentially has two parallel-connected identical circuits, designed to take complementary logic states when they receive one and the same logic level to be detected. The result of this is that the electrical comsumption of the amplifier is the same regardless of the logic level transmitted. Thus, it becomes impossible to deduce the nature of the logic level transmitted. As an improvement, the outputs of the detector are provided with bistable circuits which are coupled to each other so as to be capable of taking transitory or spurious information detected into account.

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patent: 4434381 (1984-02-01), Stewart
patent: 4563595 (1986-01-01), Bose
patent: 4593384 (1986-06-01), Kleijne
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patent: 4716320 (1987-12-01), McAdams
patent: 4724339 (1988-02-01), Ishida
patent: 4743898 (1988-05-01), Imedio
patent: 4755815 (1988-07-01), Savoyet et al.
patent: 4763023 (1988-08-01), Spence
patent: 4783801 (1988-11-01), Kaule
Ser. Nos. 07/176,335, 07/212,890 of Jacek Kowalski.

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