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Hidden control bits in a control register

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Hidden memory refresh

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Hidden refresh of a dynamic random access memory

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Hidden refresh pseudo SRAM and hidden refresh method

Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate

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Hidden self-refresh method and apparatus for synchronous dynamic

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Hiding error detecting/correcting latency in dynamic random...

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Hierarchic memory device having auxiliary lines connected to wor

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent

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Hierarchical 2T-DRAM with self-timed sensing

Static information storage and retrieval – Read/write circuit – Complementing/balancing
Reexamination Certificate

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Hierarchical bit line arrangement in a semiconductor memory

Static information storage and retrieval – Interconnection arrangements
Patent

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Hierarchical bit line bias bus for block selectable memory...

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate

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Hierarchical bitline DRAM architecture system

Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate

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Hierarchical busing architecture for a very large semiconductor

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Hierarchical column select line architecture for multi-bank DRAM

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Hierarchical common source line structure in NAND flash memory

Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate

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Hierarchical decoding of a memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent

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Hierarchical decoding of dense memory arrays using multiple...

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate

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Hierarchical depth cascading of content addressable memory...

Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate

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Hierarchical DRAM array with grouped I/O lines and high speed se

Static information storage and retrieval – Interconnection arrangements
Patent

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Hierarchical dynamic memory array architecture using read...

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Hierarchical encoder including timing and data detection devices

Static information storage and retrieval – Read/write circuit – Differential sensing
Patent

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