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Spare block management of non-volatile memories

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Spare decoder circuit

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Special mode control method for dynamic random access memory

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent

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Special mode enable transparent to normal mode operation

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Speculative sense enable tuning apparatus and associated...

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Spin momentum transfer MRAM design

Static information storage and retrieval – Read/write circuit – Including magnetic element
Reexamination Certificate

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Spin-torque bit cell with unpinned reference layer and...

Static information storage and retrieval – Read/write circuit – Including magnetic element
Reexamination Certificate

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Split read/write dynamic random access memory

Static information storage and retrieval – Read/write circuit – Simultaneous operations
Patent

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Split sense amplifier and staging buffer for wide memory archite

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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SRAM and dual single ended bit sense for an SRAM

Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate

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SRAM and testing method of SRAM

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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SRAM array with temperature-compensated threshold voltage

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate

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SRAM based cell for programmable logic devices

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Patent

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SRAM bit-line reduction

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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SRAM cell controlled by flash memory cell

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate

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SRAM cell design to improve stability

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate

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SRAM cell design to improve stability

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate

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SRAM cell with bootstrapped power line

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate

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SRAM cell with horizontal merged devices

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate

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SRAM cell with horizontal merged devices

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate

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