DRAM having self-timed burst refresh mode

DRAM having test circuit capable of performing function test of

DRAM hierarchical data path

DRAM incorporating self refresh control circuit and system LSI i

DRAM memory cell arrangement

DRAM memory cell arrangement

DRAM memory circuit with sense amplifiers

DRAM memory with a shared sense amplifier structure

DRAM operating like SRAM

DRAM output circuitry supporting sequential data capture to...

DRAM page copy method

DRAM partial refresh circuits and methods

DRAM refresh command operation

DRAM refresh control circuit

DRAM refresh timing adjustment device, system and method

DRAM refreshment

DRAM repair apparatus and method

DRAM sense amplifier having pre-charged transistor body nodes

DRAM sense amplifier having pre-charged transistor body nodes

DRAM sensing scheme and isolation circuit