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Controlling a delay lock loop circuit

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Controlling data strobe output

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Controlling multiple signal polarity in a semiconductor device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate

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Controlling the set up of a memory address

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent

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Converting dual port memory into 2 single port memories

Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate

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Count unit for nonvolatile memories

Static information storage and retrieval – Addressing – Counting
Patent

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Counter circuit, latency counter, semiconductor memory...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Counter control signal generating circuit

Static information storage and retrieval – Addressing – Counting
Reexamination Certificate

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Counting RAM

Static information storage and retrieval – Addressing – Counting
Patent

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CPU capable of modifying built-in program codes thereof and meth

Static information storage and retrieval – Addressing – Counting
Patent

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Current driver configuration for MRAM

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate

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Current mode simultaneous dual-read/single-write memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Current surge elimination for CMOS devices

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Cycle control circuit for extending a cycle period of a...

Static information storage and retrieval – Addressing – Counting
Reexamination Certificate

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Cycle independent data to echo clock tracking circuit

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Cycle ready circuit for self-clocking memory device

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Darlington type switching stage for a line decoder of a memory

Static information storage and retrieval – Addressing
Patent

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Data access circuit of semiconductor memory device

Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate

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Data access device for DRAM

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent

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Data bit assembler

Static information storage and retrieval – Addressing – Using selective matrix
Patent

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