Structure and method of implementing power savings during...

Structure of random access memory formed of multibit cells

Sub row decoder circuit for semiconductor memory device

Sub word line drive circuit for semiconductor memory device

Sub word line driving circuit

Sub word line driving circuit and a semiconductor memory device

Sub word line driving circuit and a semiconductor memory device

Sub-word line driver circuit for memory blocks of a semiconducto

Subarray control and subarray cell access in a memory module

Summation of address transition signals

Super high-speed sequential column decoder

Supply noise reduction in memory device column selection

Switch signal generators for simultaneously setting input/output

Switching circuit capable of improving memory write timing...

Switching circuit for memory devices

Sychronous semiconductor memory device with burst address counte

Synchronization circuit for a write operation on a...

Synchronization device for output stages, particularly for elect

Synchronization signal generation circuit and method

Synchronized semiconductor memory