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Selected: S

Serial access memory with column address counter and pointers

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Serial address generator for burst memory

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Serial input/output semiconductor memory

Static information storage and retrieval – Addressing – Combined random and sequential addressing
Patent

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Serial memory

Static information storage and retrieval – Addressing – Byte or page addressing
Patent

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Serial memory address decoding scheme

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate

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Serial random access memory device capable of reducing peak curr

Static information storage and retrieval – Addressing – Multiple port access
Patent

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Serial-parallel signal converter

Static information storage and retrieval – Addressing – Byte or page addressing
Patent

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Serial-parallel-serial charged coupled device memory and a metho

Static information storage and retrieval – Addressing – Byte or page addressing
Patent

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Serially accessed semiconductor memory with tapped shift registe

Static information storage and retrieval – Addressing – Sequential
Patent

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Shared dram I/O databus for high speed operation

Static information storage and retrieval – Addressing – Multiple port access
Patent

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Shared row decoder

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent

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Shared-sense amplifier control signal generating circuit in dyna

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Sharing signal lines in a memory device

Static information storage and retrieval – Addressing
Reexamination Certificate

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Shift redundancy scheme for wordlines in memory circuits

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate

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Shift register

Static information storage and retrieval – Addressing – Counting
Patent

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Signal generator with timing margin by using control signal...

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate

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Signal output device and method for the same

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Signal transfer circuit for synchronous memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Signal transition detection circuit

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Signal transition detection circuit

Static information storage and retrieval – Addressing
Patent

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