Coaxial clock tree for programmable logic devices
Cold termination for a bus
Column decoder of semiconductor memory device
Column redundancy scheme for bus-matching fifos
Columnar architecture
Columnar floorplan
Combination multiplexer and tristate driver circuit
Combination of a control unit and a logic application, in...
Combination of global clock and localized clocks
Combination of global clock and localized clocks
Combination of terminator apparatus enhancements
Combinational logic using asynchronous single-flux quantum...
Combinatorial logic circuit
Combined dynamic logic gate and level shifter and method...
Combined full speed and high speed driver
Combined logic gate and latch
Combined multiplex or/flop
Combined processing and non-volatile memory unit array
Combined tristate/carry logic mechanism
Command user interface with programmable decoder