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Selected: C

CMOS gate array with vertical transistors

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate

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CMOS high speed level shifting differential receiver

Electronic digital logic circuitry – Interface – Supply voltage level shifting
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CMOS high voltage drive output buffer

Electronic digital logic circuitry – Interface – Current driving
Patent

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CMOS I/O circuit with 3.3 volt output and tolerance of 5 volt in

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent

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CMOS I/O circuit with high-voltage input tolerance

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent

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CMOS I/O circuit with high-voltage input tolerance

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent

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CMOS implemented output buffer circuit for providing ECL level s

Electronic digital logic circuitry – Interface – Logic level shifting
Patent

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CMOS input buffer protection circuit

Electronic digital logic circuitry – Interface – Current driving
Patent

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CMOS input circuit

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent

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CMOS input circuit for providing logical output signal from TTL

Electronic digital logic circuitry – Accelerating switching
Patent

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CMOS input stage

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Patent

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CMOS input with temperature and V.sub.CC compensated threshold

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Patent

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CMOS input with Vcc compensated dynamic threshold

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Patent

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CMOS input/output control circuit capable of tolerating...

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate

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CMOS integrated circuit device and data processing system using

Electronic digital logic circuitry – Interface – Logic level shifting
Patent

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CMOS interface for coupling a low voltage integrated circuit wit

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent

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CMOS inverter

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate

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CMOS inverter and standard cell using the same

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate

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CMOS latch and register circuitry using quantum mechanical...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Diode
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CMOS level conversion circuit with input protection

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent

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