Cost saving methods using pre-defined integrated circuit...

Cost-effective scan architecture and a test application...

Cost-independent criticality-based move selection for...

Cost-independent critically-based target location selection...

Coupled noise estimation and avoidance of noise-failure...

Coupling noise reduction technique using reset timing

Coverage metric and coverage computation for verification...

Creating a PC board (PCB) layout for a circuit in which the...

Creating a power distribution arrangement with tapered metal...

Creating description files used to configure components in a...

Creating layout for integrated circuit structures

Creating optimized physical implementations from high-level desc

Creating optimized physical implementations from high-level...

Creating optimized physical implementations from high-level...

Creating photolithographic masks

Creating polynomial division logical devices

Creating standard VHDL test environments

Critical area computation of composite fault mechanisms...

Critical area computation of composite fault mechanisms...

Critical area computation of composite fault mechanisms...