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Reduced size integrated circuits and methods using test pads loc

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent

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Reduced size plate layer improves misalignments for CUB DRAM

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate

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Reduced size semiconductor package with stacked dies

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Reduced size stacked semiconductor package and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate

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Reduced soft error rate (SER) construction for integrated...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate

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Reduced stress LOC assembly

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate

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Reduced stress LOC assembly including cantilevered leads

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Beam leads
Patent

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Reduced stress plastic package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Patent

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Reduced stress terminal pattern for integrated circuit devices a

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Patent

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Reduced stress under bump metallization structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate

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Reduced stress under bump metallization structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate

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Reduced substrate capacitance high performance SOI process

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate

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Reduced substrate micro-electro-mechanical systems (MEMS)...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate

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Reduced surface field device having an extended field plate and

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent

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Reduced surface field technique for semiconductor devices

Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – In integrated circuit
Reexamination Certificate

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Reduced temperature contact/via filling

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate

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Reduced terminal testing system

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent

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Reduced terminal testing system

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate

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Reduced terminal testing system

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate

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Reduced terminal testing system

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent

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