Excavating
Patent
1986-05-15
1988-08-30
Smith, Jerry
Excavating
371 50, 371 51, G06F 1110, G06F 1120
Patent
active
047681934
ABSTRACT:
A semiconductor memory device having a main memory cell array including a plurality of rows of cell arrays, each row corresponds to a two-dimensional virtual matrix configuration. A redundancy memory cell array is provided which includes a plurality of rows of redundancy memory cells, each row corresponding to one horizontal or vertical group of memory cells of the virtual matrix configuration. When a selected memory cell is a predetermined defective cell, a row of memory cells including the defective cell is replaced with the redundancy memory cell array, thereby correcting a hard error. Also, the defective cell is accessed by an error checking and correcting circuit of a horizontal and vertical parity checking type. A horizontal or vertical group of memory cells including the selected memory cell is replaced with the corresponding row of the redundancy memory cell array, thereby correcting a soft error and a hard error other than the predetermined hard error.
REFERENCES:
patent: 4394763 (1983-07-01), Nagano
patent: 4456993 (1984-06-01), Taniguchi
patent: 4464747 (1984-08-01), Groudan
patent: 4584681 (1986-04-01), Singh
patent: 4656610 (1987-04-01), Yoshida
patent: 4688219 (1987-08-01), Takamae
IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, "Circuit Techniques for a VLSI Memory", by Mano et al., pp. 463-470.
Beausoliel Robert W.
Fujitsu Limited
Smith Jerry
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