ΔΣ modulator

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

Reexamination Certificate

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Details

C341S155000

Reexamination Certificate

active

08077066

ABSTRACT:
Disclosed herein is a ΔΣ modulator including: at least one integrator; a quantizer for quantizing a signal output by the integrator and outputting the quantized signal as a digital signal; and a compensation section configured to compensate the ΔΣ modulator for a non-ideal characteristic caused by an internal loop delay, wherein the compensation section is a feedback path formed to start at the output node of the quantizer and end at the input node of the integrator immediately preceding the quantizer, and the feedback path formed to start at the output node of the quantizer and end at the input node of the integrator realizes a frequency-independent part in combination with the integrator and an internal DA converter which adopts the NRZ technique to suppress the signal amplitude at the quantizer input.

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patent: 6388601 (2002-05-01), De Gouy et al.
patent: 6414615 (2002-07-01), Cheng
patent: 7324036 (2008-01-01), Petre et al.
patent: 7405687 (2008-07-01), Mitteregger et al.
patent: 2005/0068213 (2005-03-01), Fontaine et al.
patent: 2002-528989 (2002-03-01), None
patent: 2003-534679 (2003-11-01), None
L. J. Breems, et al., A 1.8-m W CMOS ΣΔ Modulator with Integrated Mixer for A/D Conversion of IF Signals, IEEE, Journal of Solid-State Circuits, vol. 35, No. 4, Apr. 2000.
P. Fontaine, et al., “A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop Delay,” IEEE, International Solid-State Circuits Conference, pp. 498-499, 2005.

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