Semiconductor device wiring structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257754, H01L 2348, H01L 2352, H01L 2940

Patent

active

055548881

ABSTRACT:
A semiconductor device of a multilayer wiring structure provided with a bottom conductive layer and a top conductive layer connected through a pillar connection portion, wherein the bottom conductive layer has a pattern determined by the sum of the pattern of the auxiliary conductive layer formed on the bottom conductive layer and the pattern of the pillar connection portion. Also, a process for production of a semiconductor device including a step of forming a bottom conductive layer, a step of forming an auxiliary conductive layer on the bottom conductive layer, a step of patterning just the auxiliary conductive layer to obtain a first pattern of the auxiliary conductive layer, a step of forming a pillar conductive layer on the bottom conductive layer, a step of patterning the pillar conductive layer by a predetermined second pattern to obtain a second pattern of a pillar connection portion, and a step of etching the bottom conductive layer with etching masks of the second pattern of the pillar connection portion and the first pattern of the auxiliary conductive layer to pattern the bottom conductive layer by a pattern determined by the sum of the first pattern and the second pattern.

REFERENCES:
patent: 4087314 (1978-05-01), George et al.
patent: 5132775 (1992-07-01), Bighton et al.

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