Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
A logic circuit test apparatus for testing a logic circuit having a plurality of input terminals and a plurality of output terminals, the logic circuit test apparatus including: a common test signal generating circuit which groups the input terminals of the logic circuit on the basis of logic states of original test signals to be applied to the respective input terminals of the logic circuit and outputs common test signals from common test signal output terminals thereof smaller in number than the input terminals of the logic circuit; and an input connection switching circuit which switches connections of the common test signal output terminals of the common test signal generating circuit with the input terminals of the logic circuit so as to convert the common test signals into the original test signals and apply the original test signals to the respective input terminals of the logic circuit.
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K. Chakrabarty, B..T. Murray, J. Liu and M. Zhu, “Test Width Compression for Built-in Self Testing”, Proceedings International Test Conference, IEEE Computer Society, p. 328-337, 1997.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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